PC87570-ICCSLASHVUL datasheet(104/168 Pages) NSC

104 / 168 page

ACCESS.bus (ACB) Interface

104

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13.4.4

ACB Control Register 1 (ACBCTL)

The ACBCTL1 Register is a byte-wide, read/write register

that configures and controls the ACB module. Upon reset,

the ACBCTL1 is cleared (00h)

Bit 0 - START

This bit should be set when a Start Condition needs to

be generated on the ACCESS.bus.

If the PC87570 is not the active master of the bus

(ACBST.MASTER=0), setting START generates a

Start Condition as soon as the ACCESS.bus is free

(ACBCST.BB=0). An address transmission se-

quence should then be performed.

If the PC87570 is the active master of the bus

(ACBST.MASTER=1), when START is set, a write

to the ACBSDA register generates a Start Condi-

tion, then the ACBSDA data is transmitted as the

slave’s address and the requested transfer direc-

tion.

This case is a repeated Start Condition. It may be

used to switch the direction of the data ﬂow be-

tween the master and the slave, or to choose an-

other slave device without using a Stop Condition

in between.

The START bit is cleared when the Start Condition is

sent, or on detection of a Bus Error (ACBST.BER=1).

This bit should be set only when in Master mode, or

when requesting Master mode.

Bit 1 - STOP

In master mode, setting this bit generates a Stop Condi-

tion that completes or aborts the current message trans-

fer. This bit clears itself after the STOP is issued.

Bit 2 - Interrupt Enable (INTEN)

When INTEN is cleared (0), the ACB interrupt is dis-

abled. When INTEN is set, interrupts are enabled. An in-

terrupt is generated (the interrupt signals to the ICU are

high) on one of the following events:

address

match

detected

(ACB-

ST.NMATCH=1) and NMINTE=1

A Bus Error occurs (ACBST.BERR=1)

A negative acknowledge is received after sending a

byte (ACBST.NEGACK=1).

Acknowledgment of each transaction (same as the

hardware set of the ACBST.SDAST bit).

In master mode, if ACBCTL1.STASTRE=1, after a

successful start (ACBST.STASTR=1).

Detection of a Stop Condition while in slave mode

(ACBST.SLVSTP=1).

Bit 4 - Receive Acknowledge (ACK)

When acting as a receiver, this bit holds the value of the

next acknowledge cycle. It should be set when a nega-

tive acknowledge must be issued on the next byte. This

bit is cleared (0) after the first acknowledge cycle.

This bit is ignored when in transmit mode. It cannot be

reset by software.

Bit 5 - Global Call Match Enable (GCMEN)

When this bit is set, it enables the matching of an incom-

ing address byte to the general call address (Start Con-

dition followed by address byte of 00h) while the ACB is

in slave mode. When cleared, the ACB does not re-

spond to a global call.

Bit 6 - New Match Interrupt Enable (NMINTE)

Set NMINTE to enable the interrupt on a new match

(i.e., when ACBST.NMATCH is set). The interrupt is is-

sued only if ACBCTL1.INTEN is set.

Bit 7 - Stall After Start Enable (STASTRE)

When set (1), enables the stall after start mechanism. In

such a case, the ACB stalls the bus after the address

byte. When STASTRE is cleared, ACBST.STASTR is

always cleared.

13.4.5

ACB Own Address Register (ACBADDR)

The ACBADDR Register is a byte-wide, read/write register

that holds the module’s ACCESS.bus address. The reset

value of this register is undefined.

Bits 6-0 - Own Address (ADDR)

Holds the 7-bit ACCESS.bus address of the PC87570.

When in slave mode, the first seven bits received after

a Start Condition are compared to this field (first bit re-

ceived to bit 6, and the last to bit 0). If the address field

matches the received data and ACBADDR.SAEN is 1, a

match is declared.

Bit 7 - Slave Address Enable (SAEN)

When set (1), SAEN indicates that the ADDR field holds

a valid address and enables the match of ADDR to an

incoming address byte. When cleared, the ACB does

not check for an address match.

13.4.6

ACB Control Register 2 (ACBCTL2)

The ACBCTL2 Register is a byte-wide, read/write the regis-

ter that enables/disables the module and determines ACB

clock rate. Upon reset and while the module is disabled

(ACBCTL2.ENABLE=0), the ACBCTL1 is cleared (00h).

Bit 0 - ACB Module Enable (ENABLE)

When this bit is set the ACB module is enabled. When

the Enable bit is cleared, the ACB module is disabled,

ACBCTL1, ACBST and ACBCST are cleared, and the

clocks are halted.

Bits 7-1 - SCL Frequency (SCLFRQ)

This field defines the SCL’s period (low time and high

time) when the PC87570 serves as a bus master. The

clock low time and high time are defined as follows:

tSCL =4*SCLFRQ*tCLK

tSCLl = tSCLh

210

STASTRE NMINTE GCMEN ACK

Res

INTEN STOP START

SAEN

ADDR

SCLFRQ

ENABLE

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