PC87570-ICCSLASHVUL datasheet(70/168 Pages) NSC

70 / 168 page

Real-Time Clock (RTC) and Advanced Power Control (APC)

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Table 6-4. Divider Chain Control and Bank Selection

Bit 7 - Update in Progress (UIP)

This is a read only bit which is reset at power-up reset

only.

This bit reads 0 when bit 7 of the CRB Register is 1.

1: Timing registers updated within 244

µs

0: Timing registers not updated within 244

µs

6.3.2

RTC Control Register B (CRB)

Bit 0 - Daylight Saving Enable (DSE)

This is a read/write bit which is reset at power-up reset

only.

1: Daylight saving feature enabled, as follows:

In the spring, time advances from 1:59:59 AM to

3:00:00 AM on the ﬁrst Sunday in April.

In the fall, time returns from 1:59:59 AM to

1:00:00 AM on the last Sunday in October.

0: Daylight saving feature disabled

Bit 1 - 24 or 12 Hour Mode (HM)

This is a read/write bit which is reset at power-up reset

only.

1: 24 hour format enabled

0: 12 hour format enabled

Bit 2 - Data Mode (DM)

This is a read/write bit which is reset at power-up reset only.

1: Binary format enabled

0: BCD format enabled

Bit 3 - Unused

This bit is defined as “Square Wave Enable” by the

MC146818 and is not supported by the RTC. This bit is

always read as 0.

Bit 4 - Update Ended Interrupt Enable (UIE)

This is a read/write bit that is reset to 0 on RTC reset.

1: Generation of Update Ended interrupt enabled.

This interrupt is generated when an update occurs.

0: Generation of Update Ended interrupt disabled

Bit 5 - Alarm Interrupt Enable (AIE)

This is a read/write bit that it is reset to 0 on RTC reset

(i.e., any reset and when SIBCST1.RTCMR is set).

1: Generation of Alarm interrupt enabled. This inter-

rupt is generated immediately after a time update in

which the seconds, minutes, and hours time equal

their respective alarm counterparts.

Generation of alarm interrupt disabled

Bit 6 - Periodic Interrupt Enable (PIE)

This is a read/write bit that is reset to 0 on RTC reset

(i.e., any reset and when SIBCST1.RTCMR is set)

1: Generation of Periodic interrupt enabled. Bits 3-0 of

the CRA Register determine its rate.

0: Generation of Periodic interrupt disabled

Bit 7 - Set Mode (SET)

This is a read/write bit that is reset at power-up reset

only. See also Section 6.2.10 on page 66.

1: The user copy of time is “frozen”, allowing the time

registers to be accessed whether or not an update

occurs.

0: Timing updates occur normally.

6.3.3

RTC Control Register C (CRC)

Bits 3-0 - Reserved

These bits always return 0.

Bit 4 - Update Ended Interrupt Flag (UF)

This is a read/write bit that is reset to 0 on RTC reset

(i.e., any reset and when SIBCST1.RTCMR is set). In

addition, this bit is reset to 0 when this register is read.

1: Time registers updated

0: No update occurred since the last read

Bit 5 - Alarm Interrupt Flag (AF)

This is a read/write bit that is reset to 0 on RTC reset

(i.e., any reset and when SIBCST1.RTCMR is set). In

addition, this bit is reset to 0 when this register is read.

1: Alarm condition detected

0: No alarm detected since the last read

Bit 6 - Periodic Interrupt Flag (PF)

This is a read/write bit that is reset to 0 on RTC reset

(i.e., any reset and when SIBCST1.RTCMR is set). In

addition, this bit is reset to 0 when this register is read.

1: Transition occurred on the selected tap of the divid-

er chain

0: No transition occurred on the selected tap since the

last read

DV2

DV1

DV0

Selected

Bank

Conﬁguration

CRA

Bank 0

Oscillator Disabled

Bank 0

Oscillator Disabled

Bank 0

Normal Operation

Bank 1

Normal Operation

Bank 2

Normal Operation

Undeﬁned

Test

Bank 0

Divider Chain Reset

Bank 0

Divider Chain Reset

76543210

SET

PIE

AIE

UIE

DSE

76543210

IRQF

Reserved

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