PC87570-ICCSLASHVUL datasheet(34/168 Pages) NSC

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Bus Interface Unit (BIU)

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3.0

Bus Interface Unit (BIU)

The BIU directly interfaces with a wide variety of devices, in-

cluding ROM, SRAM and FLASH memory devices and I/O

devices. It interfaces via address, data and control buses,

without the need for external glue logic.

3.1

FEATURES

Three address zones for static devices (SRAM, ROM,

FLASH, I/O)

Basic bus cycle: two clock cycles

Conﬁgurable fast read bus cycles with one-cycle read

duration

Wait states: conﬁgurable between zero and seven

clock cycles

Hold cycles: conﬁgurable between zero and three

clock cycles

I/O expansion support

Conﬁgurable burst on read

Burst read: one clock cycle

Conﬁgurable early write or late write

Bus width: conﬁgurable per zone - 16-bit or 8-bit

3.2

FUNCTIONAL DESCRIPTION

3.2.1

Interfacing

The BIU interfaces between:

The internal core bus

External static memory

Off-chip I/O (memory mapped) devices

On-chip ROM.

The BIU performs the following functions:

Distinguishes between three static memory zones

Selects the relevant conﬁgured parameters of the ac-

cessed zone (e.g., the number of wait states)

Issues the appropriate bus cycle to access the zone.

Each memory zone has a different address range and a set

of parameters which define the access to this zone. The set

of parameters is software configurable.

3.2.2

Static Memory and I/O Support

The BIU accesses static memory devices (ROM, SRAM,

FLASH and I/O devices) using static read and write bus cy-

cles. The BIU extends the bus cycles with wait cycles, if so

configured.

The BIU supports burst read bus cycles, if the accessed

zone is configured as burstable. (A burst-read bus cycle is

an extension of the basic-read bus cycle in which additional

data is accessed. A burst access usually requires only one

clock cycle per additional data item. It may be extended by

up to two clock cycles per additional data item.).

To support both I/O and static memory devices that require

long hold times at the end of the access, the BIU can be

configured to add up to three Thold clock cycles at the end

of the bus cycle. In addition to this, the BIU can be config-

ured to insert a Tidle clock cycle between two consecutive

accesses in different zones.

3.2.3

Byte Accessing

The internal core bus is 16-bit wide and supports byte and

word transactions.

The BIU issues the appropriate bus cycle to access the right

bytes, according to the core bus transaction and the memory

device bus width.

On write cycles of a single byte, the other eight bits of the bus

are floating.

On read cycles of a single byte, the other eight bits of the bus

are ignored. There is no need for external pull-up resistors.

3.3

CLOCK AND BUS CYCLES

There are two types of bus cycles: data transfer and non-

data transfer. Data-transfer bus cycles cause transfer of

data from, or to, the memory device. Non-data transfer bus

cycles (described in Section 3.4 on page 44) are used for

observability of internal bus transactions - they do not in-

volve data transfer from, or to, external devices.

There are four types of data transfer bus cycles:

Early write

Late write

Normal read

Fast read.

The BIU uses the BCFG.EWR configuration bit to select the

early or late write data transfer bus cycle. It uses the SZCF-

Gn.FRE bit (where “n” refers to zone 0 or 1) to select normal

read or fast read data transfer bus cycles.

The basic late write bus cycle takes two clock cycles. The ba-

sic early write bus cycle takes three clock cycles. When the

BIU uses the early write bus cycle, the RD signal is not re-

quired for interfacing with the memory device (with the excep-

tion of FLASH). On reset, early write bus cycle is configured.

The basic normal read bus cycle takes two clock cycles.

Fast read bus cycle always takes one clock cycle. On reset,

normal read bus cycle is configured.

Notes:

1. In the descriptions that follow, the “n” in SELn signal re-

fers to two of the three permitted BIU select signals

(numbered 0 or 1, corresponding to zone 0 or zone 1 re-

spectively). The third signal is labelled SELIO.

2. For all timing diagrams, the value of BST0-2 depends

upon the type of core bus transaction.

3.3.1

Clock Cycles

Basic Bus Cycle

A basic bus cycle comprises 1 to 3 clock cycles (depending

upon the type of bus cycle). Adding extra wait or hold clock

cycles extends the data transfer bus cycles. Every data

transfer bus cycle has the T1 and T2 clock cycles, with the

exception of the fast read bus cycle that only has one clock

cycle (T1-2).

Tidle Cycle

Clock cycles which are not used for bus cycles are called

Idle clock cycles (Tidle). Tidle cycles are added when the BIU

does not need to generate a bus transaction, or when spe-

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