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PC87570-ICC/VUL 数据表(PDF) 82 Page - National Semiconductor (TI) |
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PC87570-ICC/VUL 数据表(HTML) 82 Page - National Semiconductor (TI) |
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82 / 168 page  Interrupt Control Unit (ICU) 82 www.national.com Table 9-2. Interrupt Assignment List 1. To enable the external interrupt, set the pin to its alternate function. When used as I/O port signals the External interrupt input is forced to 0. 2. This interrupt is an OR of the two MIWU outputs. When no WKINTA is an input, disable it by clearing the respec- tive bit in WKEN1. When the APC-OFF event is not in use, disable it by clearing the CST2.APCOFFE bit. 3. When in Active mode, you should disable the T0OUT channel of the MIWU, if not required. This saves the need to clear the pending bit in the MIWU on each interrupt. 4. INT10 is the logic OR of EXINT10 after the MIWU and PSINT3. For efficient operation, only one of them should be enabled at a time. 5. INT11 is the logic OR of EXINT11 after the MIWU and PSINT2. For efficient operation, only one of them should be enabled at a time. 9.3 ICU REGISTERS 9.3.1 NMI Status Register (NMISTAT) The NMISTAT Register is a byte-wide, read only register. It holds the status of the PFAIL NMI request. NMISTAT is cleared each time its contents are read. Non-reserved bits of NMISTAT are cleared on reset. Bit 0 - Power Fail Input (PFAIL) PFAIL indicates that a falling edge was detected on the PFAIL pin. 9.3.2 Power Fail Control Register (PFAIL) The PFAIL Register is a byte-wide read/write register. It pro- vides control over the early power fail indication NMI. This register is cleared by hardware on reset. Bit 0 -PFAIL Trap Enable (EN) An NMI trap is generated when the EN bit is set, and the PFAIL pin changes its value from high to low. The bit is cleared by hardware on reset, and whenever the trap occurs. The EN bit can be set and cleared by PC87570’s firmware. Interrupt Source Type Description Priority INT0 External External Interrupt 0 (EXINT0)1, through the MIWU Lowest INT1 Internal High Level Host I/F Keyboard/Mouse channel output buffer empty INT2 Internal High Level Host I/F Power Management channel output buffer empty INT3 Internal High Level MIWU WKINTA (PS2, APC-ON, ACCESS.bus wakeup) or WKO24 (APC-OFF 2) INT4 Internal High Level MFT16 interrupt (INT1 OR’ed with INT2) INT5 Internal High Level ADC interrupt INT6 Internal High Level ACCESS.bus interrupt INT7 Internal High Level MIWU WKINTC Internal Keyboard Scan Interrupt (KBSINT) INT8 Internal Rising Edge TWM system tick (T0OUT), through the MIWU 3 INT9 External SWIN input 1, through the MIWU INT104 Internal Falling Edge PS/2 interface channel 3 (PSINT3) External External interrupt 10 (EXINT10) 1, through the MIWU INT115 Internal Falling Edge PS/2 interface channel 2 (PSINT2) External External interrupt 11 (EXINT11) 1, through the MIWU INT12 Internal High Level PS/2 shift mechanism (PSINT1) Internal Falling Edge PS/2 interface channel 1 INT13 Internal High Level Host I/F Keyboard/Mouse IBF INT14 Internal High Level Host I/F Power Management IBF INT15 External External interrupt 15 (EXINT15) 1, through the MIWU Highest 7 1 0 Reserved PFAIL 7 2 1 0 Reserved PIN EN |
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