PC87570-ICCSLASHVUL datasheet(44/168 Pages) NSC

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Bus Interface Unit (BIU)

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3.3.8

I/O Expansion Example

Figure 3-14 shows an example of how two ports can be im-

plemented off-chip, using I/O expansion. This example im-

plements two 8-bit ports, by connecting the SELIO, RD and

WR0 pins to the latch/buffer controls.

3.4

DEVELOPMENT SUPPORT

The BIU provides the following support for development

systems.

3.4.1

Bus Status Signals

The Bus Status BST0-2 signals indicate whether a transac-

tion on the core bus was issued, and the transaction type.

See Table 18-1 on page 130.

3.4.2

Core Bus Monitoring

The core bus monitoring cycle is a non-data transfer bus cy-

cle. It takes a single clock cycle - T1. On this cycle:

• The address pins display the address of the internal de-

vice accessed on the core bus.

• CBRD indicates the direction of the access (read or

write).

• BE0-1 indicate which data bus bytes are accessed (low-

er or upper).

• BST0-2 display the core bus status.

See Figure 3-15. The core bus monitoring cycle is generat-

ed only when the BCFG.OBR configuration bit is 1.

SELIO1

PC87570

74x377

74x541

OE1

OE2

WR01

CP 8-Bit

D-FF

8-Bit

Buffer

Figure 3-14. Example of an Implementation of Two Ports Using I/O Expansion

1. This routing is for late write. If early write, SELIO is routed to CP and WR0 to CE. All other routing is unchanged.

D0-7

CLK

A0-12,

SEL0-1

WR0-1

D0-15

BST0-2

SELIO

A16-18

CBRD

BE0-1

Figure 3-15. Core Bus Monitoring Bus Cycle

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