PC87570-ICCSLASHVUL datasheet(26/168 Pages) NSC

26 / 168 page

Signal/Pin Connection and Description

www.national.com

2.3

RESET SOURCES AND TYPES

2.3.1

Power-Up Reset

The PC87570 includes an internal power-up reset circuit

This circuit generates the power-up reset signal which

During power-up reset, the PC87570 responds as follows:

Carries out all the warm reset actions

Enables the 32K crystal, if it is disabled

Resets the HFCG Register to its default frequency

Loads preset values to all register.

Puts pins with strap options into TRI-STATE, and en-

ables the internal pull-downs on the strap pins

Samples the values of the strap pins.

2.3.2

Warm Reset

During a warm reset, the PC87570 responds as follows:

Terminates instructions being executed

Discards results not yet written to memory

Traps and eliminates pending interrupts

Clears the internal latch for the edge-sensitive external

interrupt

Deactivates the external bus control signals WR(0-1),

SEL(0-1), SELIO, RD and BST(0-2)

Puts the address A(0-15) and data D(0-15) buses in

TRI-STATE

Switches to Active mode

Loads preset values into registers

Sets the motherboard PnP mechanism to its reset

state.

Certain registers, such as the HFCG and Port PC Registers,

are affected only by power-up and/or WATCHDOG reset.

During warm reset, the strap pins are not sampled and the

configuration determined at power-up is unaffected by sub-

sequent warm resets.

2.3.3

WATCHDOG Reset

During a WATCHDOG reset, the PC87570 performs the

power-up reset actions with one exception: it does not sam-

ple the value of the strap pins. Instead, it maintains the con-

figuration determined by the strap pins at power-up reset.

2.3.4

Triggering Reset

The PC87570 is reset by an internal reset signal generated

on the ramp-up of the VCC power supply (cold reset). The

chip is also reset on the rising edge of the HMR pin (warm

reset).

Power-Up Reset The PC87570 performs a power-up reset

when power is applied to it. This reset is completed tIRST af-

ter the internal clock has stabilized. See Figure 19-25 on

page 154.

If the RTC clock was disabled before power-up, external de-

vices should wait at least t32KW (see before accessing the

PC87570. If HRMS=0, any access by the host processor is

stalled, by de-asserting (0) HIOCHRDY, until after the reset

process is completed and the bus request can be per-

formed.

Warm Reset A rising edge of the HMR input initiates a

warm reset. The rising edge is identified only when power

(VCC) is applied to the PC87570 completed the internal

power-up reset cycle. The reset continues for a period of

about 16 clock cycles after the HMR rising edge. See details

at Figure 19-26 on page 154.

The PC87570 can operate when HMR is still active (high).

In this case, the host bus I/F is inactive.

Note: In all PC87570 revisions, before C3, the HMR (for-

merly HMR) input pin is ignored when HPWRON is 0, dis-

abling reset execution.

WATCHDOG Reset

The PC87570 generates a WATCHDOG reset on request

from the TWD (WATCHDOG signal is asserted). The reset

period is identical to the power-up reset period.

2.4

STRAP PINS

During power-up reset, the ENV(0-1), TRIS, HRMS, HDEN

and SHBM strap input signals are sampled. Internal pull-

down resistors set these signals to 0. You can use an exter-

nal 10 K

Ω resistor connected to V

CC to set them to 1.

2.4.1

Setting the Environment

ENV0 and ENV1 determine the operating environment. Ta-

ble 2-3 shows the settings allowed. Pulling both ENV0 and

ENV1 to 1 at the same time produces unpredictable results.

Table 2-3. Environment Pin Settings

Figures 1-1 on page 16, 1-2 on page 17, and 1-3 on page

18 demonstrate how to use the ENV(0-1) signals to config-

ure the PC87570 for IRE, IRD, and Dev environment, re-

spectively.

2.4.2

Other Strap Pin Settings

Table 2-4 provides brief descriptions of other strap inputs.

For details on SHBM, HRMS, HDEN and TRIS, see sec-

tions 5.2 on page 49, 5.11.4 on page 53, 5.11.5 on page 54

and 18.2 on page 130, respectively.

Table 2-4. Other Strap Pin Settings

Environment

ENV0

ENV1

IRE

IRD

Dev

Strap

Internal Pull-Down (0)

External Pull-Up (1)

SHBM Enables shared memory

with host BIOS

Disables shared

memory with host BIOS

HRMS Extends host access

until the PC87570

completes its execution

Enables a reset event to

be sent to the host

when the shared BIOS

is accessed while the

PC87570 is not in

Active mode, or SHOFF

or SHMEM bit is cleared

in MCFG Register

PC87570-ICC/VUL 数据表(PDF) 26 Page - National Semiconductor (TI)

PC87570-ICC/VUL 数据表(HTML) 26 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载