PC87570-ICCSLASHVUL datasheet(29/168 Pages) NSC

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Signal/Pin Connection and Description

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1. PB5 is initialized upon reset as an output port with data set to 1. This allows the

PC87570 ﬁrmware to use it as GA20.

2. PB6 is always conﬁgured as output and with its alternate function enabled. See

Section 5.11.4 on page 53.

2.6

SYSTEM CONFIGURATION REGISTERS

2.6.1

Module Configuration Register (MCFG)

The MCFG Register is a read/write, byte-wide register. It is

used for global system configuration and setup.

Write operations to the MCFG Register should write zeros

to all reserved bits. Upon reset, non-reserved bits of MCFG

are cleared to 0. MCFG can be written in Active mode only.

Its contents is preserved in Idle mode.

In IRE environment, all fields of MCFG should be used to

designate associated pins as GPIO ports or for their alter-

nate functions. In IRD and Dev environments, the pins are

always allocated for IRD or Dev use. The I/O ports function-

ality can be implemented using off-chip logic.

To guarantee binary and cycle-by-cycle compatibility

among the different environments, define the MCFG fields

as required for IRE even when in IRD or Dev environments,

and use the I/O Expansion protocol to build an off-chip im-

plementation of the I/O ports when they are used by the ap-

plication.

ADBs or ISE systems may use the MCFG Shadow (MCFG-

SH) Register to select the functionality of the signal that

reaches the user’s application.

Bit 0 - Base Memory Shadow Off (SHOFF)

While cleared, the Base Memory can be accessed start-

ing from address 10000h and the External Memory can-

not be accessed. When set, this signal turns off the

Base Memory shadow (i.e., the copy that starts at ad-

dress 00000h) and enables access to the External

Memory. Once SHOFF is set, the firmware should not

clear it.

Bit 1 - Shared Memory Access Enable (SHMEM)

The host processor is enabled to access the shared

memory only when SHMEM and SHOFF are set. Addi-

tional conditions to the host access are described in

Sections 2.7 on page 30 and 5.2 on page 49. When

SHMEM is cleared the host access to the shared mem-

ory is disabled. Once SHMEN is set, the firmware

should not clear it.

Bit 2 - External Memory 16-Bit (EXM16)

While cleared, it defines the External Memory as 8 bits

wide. When set it enables the use of a 16-bit wide Exter-

nal Memory. The bus width as indicated in this register

and the bus width as defined in zone0 of the BIU

(SZCFG0) should be the same.

When a 16-bit wide External Memory is used, ports

PF0-7 and PG4 serve as part of the memory interface.

PG0/SELIO

PG0

I/O

SELIO

Dev or IRD Env;

IRE Env when

MCFG.EXIOE=1

PG1/A15/CBRD

PG1

A15/CBRD

Dev or IRD Env;

IRE Env when

MCFG.A15E=1

PG2/CLK

PG2

CLK

Dev or IRD Env;

IRE Env when

MCFG.CLKOE=1

PG3/SEL1

PG3

SEL1

Dev or IRD Env;

IRE Env when

MCFG.EXM16=1

PG4/WR1

PG4

WR1

PH0/BST0/ENV0

PH0

I/O

BST0

Dev Env

PH1/BST1/ENV1

PH1

BST1

PH2/BST2

PH2

BST2

PH3/PFS

PH3

PFS

PH4/PLI

PH4

PLI

PH5/ISE

PH5

ISE

Pin Name

Port Signal

Alternate

Function

Select

(Alternate Function)

Name

Type

Res

CLKOE EXIOE A15E EXM16 SHMEM SHOFF

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