PC87570-ICCSLASHVUL datasheet(73/168 Pages) NSC

73 / 168 page

Real-Time Clock (RTC) and Advanced Power Control (APC)

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6.6.1

APC Control Register 1 (APCR1)

Bits 4-0 - Reserved

Bit 5 - Software Off Command (SOC)

This bit is write-only and non-sticky. Read returns 0.

0: Ignored

1: APC-OFF interrupt signal generated

Bit 6 - Reserved

Bit 7 - Power Off (PF)

This bit is set to 1 when RTC/APC switches from VCC to

VBAT. Cleared to 0 by writing 1 to this bit. Writing 0 to this

bit has no effect.

6.6.2

APC Control Register 2 (APCR2)

Bit 0 - Time Match Enable (TME)

0: Pre-determined date or time event ignored

1: APC-ON interrupt generated on a match between

the RTC and the pre-determined date or time

Bit 1 - Reserved

Bit 2 - RING Pulse or Train Detection Mode (RPTDM)

0: RING pulse falling edge detected

1: RING pulse train > 16 Hz for 0.19 s

Bit 3 - RING Enable (RE)

RING input signal ignored

1: APC-ON interrupt generated on RING detection

Bits 7-4 - Reserved

6.6.3

APC Status Register (APSR)

The bits in this register that detect events are cleared to 0

when this register is read.

Bit 0 - Timer Match Detect (TMD)

This bit is set to 1 when the RTC reaches the pre-deter-

mined date, regardless of the value of the TME bit (bit 0

of APCR2).

Bit 1 - RING Detect (RID)

This bit is set to 1 when a RING pulse or RING pulse

train is detected on the RING input pin, regardless of the

value of the RE bit (bit 3 of APCR2).

Bits 6-2 - Reserved

Bit 7 - RING Status (RS)

Holds the instantaneous value of the RING pin.

6.6.4

RAM Lock Register (RLR)

Once a non-reserved bit is set to 1, it can be cleared only by

a hardware (HMR pin) reset.

Bits 2-0 - Reserved

Bit 3 - Upper RAM Block (URB)

Controls access to the upper 128 RAM bytes, accessed

via the Upper RAM Address and Data Ports of Bank 1

0: No effect on upper RAM access

1: Upper RAM Data Port of Bank 1 blocked; writes are

ignored and reads return FFh

Bit 4 - RAM Block Read (RBR)

This bit controls reads from Upper RAM bytes 00h-1Fh.

0: No effect on upper RAM access

1: Reads from bytes 00h-1Fh of upper RAM return

FFh

Bit 5 - RAM Block Write (RBW)

This bit controls writes to bytes 00h-1Fh of upper RAM.

0: No effect on upper RAM access

1: Writes to bytes 00h-1Fh of upper RAM ignored

Bit 6 - RAM Mask Write (RMW)

This bit controls writes to all RTC RAM.

0: No effect on RAM access

1: Writes to bytes 0Eh-3Fh of all banks, bytes 40h-

7Fh of Bank 0 and to all upper RAM ignored

Bit 7 - RAM Lock (RL)

0: No effect on RAM access

1: Read and write to locations 38h-3Fh of all bank

blocked; writes ignored and reads return FFh.

Res

SOC

Reserved

3210

Reserved

RPTDM

Res

TME

Reserved

RID

TMD

76543

RMW

RBW

RBR

URB

Reserved

PC87570-ICC/VUL 数据表(PDF) 73 Page - National Semiconductor (TI)

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