PC87570-ICCSLASHVUL datasheet(63/168 Pages) NSC

63 / 168 page

Host Bus Interface (HBI)

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1: A read or write access by the host to the address

speciﬁed by KBCCSAH, KBCCAL generates a chip

select to the KBC channel (HKBCCS).

Bit 2 - PM Enable (PME)

0: PM channel cannot be accessed by the host; i.e.,

access to the address speciﬁed in PMCSAH, PMC-

SAL does not generate a chip select.

1: A read or write access by the host to the address

speciﬁed by PMCSAH, PMCAL generates a chip se-

lect to the PM channel (HPMCS).

5.14.13 Function Lock Register (FLR)

The FLR Register provides a lock bit to protect the configu-

ration registers from further change. This lock bit is for any

one of the host interface functions. On reset, the FLR Reg-

ister is cleared, enabling writes to all registers. Writing 1 to

a bit in the register locks the corresponding function. Once

locked, a function cannot be unlocked until reset is applied.

Bit 0 - RTC Channel Conﬁguration Lock (RTCLK)

0: RTC

conﬁguration

may

changed;

i.e.,

RTCCSAH and RTCCSAL Registers and RTCE in

the FER Register may be written.

1: RTC

conﬁguration

cannot

changed;

i.e.,

RTCCSAH and RTCCSAL Registers and RTCE in

the FER Register become read only. Any data writ-

ten to them is ignored.

Bit 1 - KBC Channel Conﬁguration Lock (KBCLK)

0: Keyboard channel conﬁguration may be changed;

i.e., KBCCSAH and KBCCSAL Registers and

KBCE in the FER Register may be written.

1: Keyboard

channel

conﬁguration

cannot

changed; i.e., KBCCSAH and KBCCSAL Registers

and KBCE in the FER Register become read only.

Any data written to them is ignored.

Bit 2 - PM Channel Conﬁguration Lock (PMLK)

0: PM channel conﬁguration may be changed; i.e.,

PMCSAH and PMCSAL Registers and PME in the

FER Register may be written.

1: PM channel conﬁguration cannot be changed; i.e.,

PMCSAH and PMCSAL Registers and PME in the

FER Register become read only. Any data written

to them is ignored.

Bit 7 - Base Address Conﬁguration Lock (SBALK)

0: Address of the conﬁguration Index and Data Registers

may be changed; i.e., SBAL and SBAH may be written.

1: Conﬁguration Index and Data Registers address

cannot be changed; i.e., SBAL and SBAH become

read only. Any data written to them is ignored.

5.14.14 IRQ Enable Register (IRQE)

The IRQE Register allows the host to enable the interrupt

signals. On reset, this register is set according to the value

of HDEN. If HDEN=0, it is cleared, disabling all interrupts by

placing the pins in TRI-STATE. If HDEN=1, non-reserved

bits in the IRQE Register are set to enable the interrupts.

For a description of the various IRQ modes, see Section

5.10.

Bit 0 - Interrupt Request 1 Enable (IRQ1E)

0: IRQ1 is in TRI-STATE

1: IRQ1 signal is active, according to the mode select-

ed.

Bit 1 - Interrupt Request 12 Enable (IRQ12E)

0: IRQ12 is in TRI-STATE

1: IRQ12 signal is active, according to the mode se-

lected.

Bit 2 - Interrupt Request 11 Enable (IRQ11E)

0: IRQ11 is in TRI-STATE

1: IRQ11 signal is active, according to the mode se-

lected.

Bit 3 - Interrupt Request 8 Enable (IRQ8E)

0: IRQ8 is in TRI-STATE

1: IRQ8 signal is active, according to the mode select-

ed.

SBALK

Reserved

PMLK KBCLK RTCLK

7654

Reserved

IRQ8E IRQ11E IRQ12E IRQ1E

PC87570-ICC/VUL 数据表(PDF) 63 Page - National Semiconductor (TI)

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