PC87570-ICCSLASHVUL datasheet(52/168 Pages) NSC

52 / 168 page

Host Bus Interface (HBI)

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5.7

PM CHANNEL

The PM channel structure is almost identical to the structure

of the PS/2 channel (see Figure 5-3), with two differences:

their addresses; the PM channel generates only one inter-

rupt to the host.

The host interface of the PM function is compatible with

8051SL interface. Its structure and operation are similar to

those of the KBC channel., with the following differences:

Host addresses at 62 and 66 (default)

One IRQ issue (IRQ11) on output buffer full

The core has one address for the output buffer

Control bits and interrupts are separated by different names

(see Figure 5-3 and register descriptions).

5.8

RTC/APC CHANNEL

The RTC/APC channel enables communication with this

module from both the host and the CR16A by using an In-

dex and Data register pair. Upon reset, the host can access

these registers at 0070h and 0071h. For more information,

please refer to Section 6.2.1.

5.9

CR16A INTERRUPTS

The host interface generates four level interrupts to the ICU.

These can be used by the firmware for an interrupt driven

control of the KBC and/or PM channels.

5.10 HOST INTERRUPTS

The HBI supports four interrupts to the host:

Keyboard interrupt, IRQ1

Mouse interrupt, IRQ12

PM interrupt, IRQ11

RTC/APC interrupt, IRQ8

These interrupts may be controlled by the hardware accord-

ing to the status of the host interface buffers or when the

PC87570 firmware toggles the bit value.

When IRQ1, IRQ12 and/or IRQ11 are disabled (OBFKIE,

OBFMIE and/or PMHIE in the HICTRL Register are

cleared), the firmware can control the IRQ1, IRQ12 and

IRQ11 signals by writing to the signal’s respective bit in the

HIIRQC Register. When IRQ1, IRQ12 and/or IRQ11 are

controlled by hardware (OBFKIE, OBFMIE and/or PMHIE in

the HICTRL Register are set to 1), interrupt to the host is

generated according to the status of OBF in the HIKMST

In normal polarity mode (IRQNPOL in the HIIRQC Register

is 0), the PC87570 supports two types of interrupts: edge or

level. When an edge interrupt is selected (IRQM in the HI-

IRQC Register is not 0), the interrupt signal default value is

high (1). When an interrupt signal needs to be sent (i.e., the

corresponding OBF flag is set), a negative pulse is generat-

ed. The pulse width is determined by IRQM.

When a level interrupt is selected, (IRQM in the HIIRQC

asserted (1) to indicate that the respective OBF flag is set.

The signal is de-asserted (0) when the output buffer is read

(i.e., the corresponding OBF flag is cleared).

Note that IRQ1 and IRQ12 have the same OBF flag but are

asserted separately. Either IRQ1 or IRQ12 is set, depend-

ing on the internal register written (HIKDO or HIMDO, re-

spectively).

In negative polarity mode (when IRQNPOL of the HIIRQC

posite from normal polarity mode.

The PC87570 firmware can read IRQ1, IRQ12 and IRQ11

pins’ value by performing a read operation from IRQ1B,

IRQ12B and IRQ11B in the HIIRQC Register.

STATUS

D0-7

Input

Output

Interrupts to CR16A

IRQ11

Peripheral Bus

Resident Device Bus

Interrupt to the host

Figure 5-3. PM Channel

DBBOUT

DBBIN

Buffer

Empty

Buffer

Full

(PM)

0062h

0066h

STATUS

COMMAND

DATA

HIPMST

FEACh

HIPDO

FEAEh

HIPMDI

FEB0h

PC87570-ICC/VUL 数据表(PDF) 52 Page - National Semiconductor (TI)

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