PC87570-ICCSLASHVUL datasheet(86/168 Pages) NSC

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Multi-Input Wake-Up (MIWU)

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The MIWU is active while in Idle state. In this state, all

clocks of the device are stopped. Therefore the detection of

a trigger condition on an input, and the resulting set of the

pending flag, are not synchronous to the system clock.

10.2.1

Trigger Conditions

Through the WKEDGx registers you can select the trigger

condition on the selected input signal as either positive

edge (low-to-high transition) or negative edge (high-to-low

transition).

10.2.2

Pending Flags

An occurrence of the selected trigger condition for the

MIWU is latched into a pending register, WKPNDx. The re-

spective bits of WKPNDx are set on an occurrence of the

selected trigger edge on the corresponding input signal.

Since the WKPNDx register holds a pending wake-up con-

dition until it is cleared, the device does not enter the Idle

state if any wake-up bit is both enabled and pending. Con-

sequently, you must clear the pending flags before attempt-

ing to enter the Idle state.

10.2.3

Input Enable

The MIWU utilizes multiple multi-input wake-up signals.

Setting the appropriate bits in the WKENx registers selects

which particular wake-up signal causes the device to exit

the Idle state.

10.2.4

Interrupts

The combined output of all pending and enabled channels

of the MIWU module generates the wake-up signal which is

fed into both the PM module and the ICU. Therefore, each

wake-up of the device, except for wake-up on host access,

can be followed by a wake-up interrupt. Since the device

cannot enter some of the power reduction states without the

CR16A executing a WAIT instruction, the wake-up interrupt

must terminate the WAIT instruction on wake-up.

The MIWU module also provides signal conditioning and

grouping of events which can be used to generate interrupt

requests.

WKO20-WKO25 and WKO27 are connected to the ICU to

generate an interrupt associated with the specific MIWU

output. The WKOx behaves as follows:

When WKENx is cleared, the WUIx is connected to

the ICU directly (bypassing the edge detectors and

pending bits). The ICU can be conﬁgured for using the

signal as a level or edge triggered interrupt.

When WKENx is enabled, the output of the pending

bit, WKPNDx is connected to WKOx.

The Mask Register in the ICU enables/disables Interrupts

caused by WKOx. In addition, the MIWU provides interrupt

request lines WKINTA and WKINTC (see Figure 10-1).

These are routed to the ICU, and can request an interrupt if

a valid trigger condition occurred on any of the enabled in-

put sources within a group of eight.

10.2.5

Input Assignments

For information on MIWU input assignments, including a

detailed device-specific summary, see Table 10-1.

10.3 MIWU REGISTERS

10.3.1

Edge Detection Register 1(WKEDG1)

The WKEDG1 Register is a byte-wide, read/write register

that configures the trigger condition of the input signals

WUI10 to WUI17. The register is cleared on reset. This con-

figures all associated input signals to be triggered on a fall-

ing edge.

Bits 7-0 - Wake-Up Edge Selection (WKEDG17-10)

For inputs WUI17 through WUI10. Each bit is associat-

ed with one of eight inputs.

0: Low-to-high transition

1: High-to-low transition

10.3.2

Edge Detection Register 2 (WKEDG2)

The WKEDG2 Register is a byte-wide, read/write register

that configures the trigger condition of the input signals

WU20 to WU27. The functionality of the register is identical

to the WKEDG1 Register described above.

10.3.3

Edge Detection Register 3 (WKEDG3)

The WKEDG3 Register is a byte-wide, read/write register

that configures the trigger condition of the input signals

WU30 to WU37. The functionality of the register is identical

to the WKEDG1 Register described above.

10.3.4

Pending Register 1 (WKPND1)

The WKPND1 Register is a byte-wide, read/write register

that latches the occurrence of a selected trigger condition

associated with the input signals WUI10 to WUI17. On re-

set, WKPND1 Register is cleared (0). This indicates that no

occurrence of the selected trigger condition is pending.

Note:

While software can set the register bits, only the WKPCL1

their values unchanged.

Bits 7-0 - Wake-Up Pending (WKPND17-10)

If set, indicates that a valid trigger condition has oc-

curred on the associated input.

10.3.5

Pending Register 2 (WKPND2)

The WKPND2 Register is a byte-wide, read/write register

that latches the occurrence of a selected trigger condition

associated with the input signals WUI20 to WUI27. For a

detailed description of the register see the above descrip-

tion of the WKPND1 Register.

WKEDG17-WKEDG10

WKPND17-WKPND10

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