PC87570-ICCSLASHVUL datasheet(57/168 Pages) NSC

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Host Bus Interface (HBI)

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Bit 0 - Host Interrupt Request 1 Control (IRQ1B)

When the IRQ1 signal is configured for direct control by

the firmware (OBFKIE in the HICTRL Register is 0), this

bit directly controls the state of IRQ1 pin. When read,

IRQ1B returns the current value of the IRQ1 pin, which

can be read regardless of the state of OBFKIE.

Bit 1 - Host Interrupt Request 12 Control (IRQ12B)

When the IRQ12 signal is configured for direct control

by the firmware (OBFMIE in the HICTRL Register is 0),

this bit directly controls the state of IRQ12 pin. When

read, IRQ12B returns the current value of the IRQ12

pin, which can be read regardless of the state of

OBFMIE.

Bit 2 - Host Interrupt Request 11 Control (IRQ11B)

When the IRQ11 signal is configured for direct control

by the firmware (PMHIE in the HICTRL Register is 0),

this bit directly controls the state of IRQ11 pin. When

read, IRQ11B returns the current value of the IRQ11

pin, which can be read regardless of the state of PMHIE.

Bits 5-3 - IRQ Mode (IRQM)

Sets the hardware controlled IRQ signals to work in lev-

el or pulse mode and defines the pulse width in the

pulse modes.

When IRQM = 0002, the IRQ signals function in a level

mode. In this mode when IRQNPOL bit below is 0, the

IRQ signals default value is low, and a high level is set

to issue an interrupt (the respective OBF is set).

When IRQM

≠0, the host interrupts are in pulse mode.

When IRQNPOL bit below is 0, the IRQ signals default

value is high, and it toggles low to issue an interrupt (i.e.,

when the respective output buffer register is written).

See Table 5-3 for the pulse widths.

Table 5-3. IRQM Pulse Modes

Bit 6 - IRQ Negative Polarity (IRQNPOL)

0: IRQ signal (IRQ1, IRQ11, IRQ12) polarity is com-

patible with the standard ISA bus interface.

1: When hardware IRQ generation is enabled (when

OBFKIE, OBFMIE or PMHIE for IRQ1, IRQ12 or

IRQ11, respectively in the HICTRL Register are

set), the interrupt output is inverted.

Bit 7 - Push Pull Enable (PSPE)

0: IRQ signals (IRQ1, IRQ11 and IRQ12) output driv-

ers are open drain type. Therefore, when an output

logic is 0, the signal is pulled low; when output logic

is 1, the signal is ﬂoating and its level is set by the

system. External pull-up resistors should be used.

1: IRQ signals drivers are full push-pull drivers.

Therefore, the PC87570 drives the signals for both

low and high levels.

5.12.8

Host Interface KBC Status Register (HIKMST)

The HIKMST Register is a byte wide, read/write register. It

provides the status of the host interface keyboard channel

buffers (DBBIN and DBBOUT) and a means for the

PC87570 to send status bits to the host. This register can

also be read by a host read operation from address 64h.

HIKMST is cleared (00h) on reset.

Bit 0 - Output Buffer Full (OBF)

This bit is a read only bit and is ignored when writing to

this register.

0: Host reads from the KBC channel output buffer

(60h)

1: KBC channel’s DBBOUT is written by the CR16A

(writing to the HIKDO or HIMDO Registers)

Bit 1 - Input Buffer Full (IBF)

This bit is a read only bit and is ignored when writing to

this register.

0: CR16A reads input buffer (HIKMDI Register)

1: KBC channel’s DBBIN is written by the host (writing

to either address 60h, data, or address 64h, con-

trol) T

Bit 2 - Flag 0 (F0)

A general-purpose flag that can be set or cleared by the

CR16A firmware.

Bit 3 - A2 Address (A2)

Holds the value of the HA2 line in the last write operation

of the host to the KBC channel’s input buffer (i.e., indi-

cates HA2 value during write to address 60h or 64h).

This bit is a read only bit and is ignored when writing to

this register.

Bits 7-4 - Status Bits 0-3 (ST0-3)

Four general-purpose flags that can be set or cleared by

the CR16A firmware.

5.12.9

Host Interface Keyboard Data Out Buffer

The HIKDO Register is a byte wide, write only register. It al-

lows the CR16A firmware to write to the DBBOUT Register,

while setting OBF in the HIKMST Register. If enabled, IRQ1

IRQM

Mode

0002

Level Interrupt

0012

1-cycle Pulse

0102

2-cycle Pulse

0112

4-cycle Pulse

1002

8-cycle Pulse

1012

16-cycle Pulse

Other

Reserved

76543210

ST3

ST2

ST1

ST0

IBF

OBF

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