PC87570-ICCSLASHVUL datasheet(45/168 Pages) NSC

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Bus Interface Unit (BIU)

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3.5

BIU REGISTERS

3.5.1

BIU Configuration Register (BCFG)

The BCFG Register is a byte-wide, read/write register that

controls the configuration of common features to all zones.

On reset, BCFG is initialized to 07h.

Bit 0 - Early Write or Late Write (EWR)

0: Late Write

1: Early Write

Bit 1 - Observability (OBR)

Address and Status Observability of Internal Accesses.

0: Address and status of internal accesses are not

observable. No toggle of external buses.

1: Address and status of internal accesses are ob-

servable. External buses toggle.

3.5.2

I/O Zone Configuration Register (IOCFG)

The IOCFG Register is a word-wide, read/write register that

controls the configuration of the I/O zone. On reset, IOCFG

is initialized to 069Fh.

Bits 2-0 - WAIT

Number of TIW clock cycles that extend the bus cycle.

000: None

001: One

010: Two

011: Three

100: Four

101: Five

110: Six

111: Seven

Bits 4,3 - HOLD

Number of Thold clock cycles.

00: None

01: One

10: Two

11: Three

Bit 7 - Bus Width (BW)

BW defines the external bus-width used for the I/O

zone. Bus width is initialized during reset to its default

value.

0: 8-bit bus

1: 16-bit bus (default)

Bit 9 - Post Idle (IPST)

An idle cycle follows the current bus cycle, when the

next bus cycle is in a different zone

0: No idle cycle inserted

1: Idle cycle inserted

3.5.3

Static Zone Configuration Register (SZCFGn)

The SZCFGn Register (where n = 0 or 1) is a word-wide,

read/write register that controls the configuration of zone n.

On reset, SZCFGn is initialized to 069Fh.

Bits 2-0 - WAIT

Number of TIW clock cycles that extend the bus cycle.

000: None

001: One

010: Two

011: Three

100: Four

101: Five

110: Six

111: Seven

These bits are ignored when SZCFGn.FRE bit is 1.

Bits 4,3 - HOLD

Number of Thold clock cycles.

00: None

01: One

10: Two

11: Three

These bits are ignored when SZCFGn.FRE bit is 1.

Bit 5 - Burst Read Enable (BRE)

0: Disabled

1: Enabled

This bit is ignored when SZCFGn.FRE bit is 1.

Bit 6 - Wait on Burst Read WBR)

WBR determines if a wait state is added on Burst Read

transaction.

0: No TBW on burst read cycles

1: TBW on burst read cycles

This bit is ignored when SZCFGn.FRE bit is 1 or when

SZCFGn.BRE is 0.

Bit 7 - Bus Width (BW)

BW defines the width of the external bus used for the

zone. BW is initialized during reset to its default value.

0: 8-bit bus

1: 16-bit bus (default)

Reserved

OBR

EWR

Reserved

IPST

Res

5 4

3 2

Reserved

HOLD

WAIT

Reserved

FRE

IPRE

IPST

Res

7654

WBR

BRE

HOLD

WAIT

PC87570-ICC/VUL 数据表(PDF) 45 Page - National Semiconductor (TI)

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