 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
PC87570-ICC/VUL 数据表(PDF) 68 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87570-ICC/VUL 数据表(HTML) 68 Page - National Semiconductor (TI) |
|
|
68 / 168 page  Real-Time Clock (RTC) and Advanced Power Control (APC) 68 www.national.com 6.2.13 System Bus Lockout During power-up or power-down, spurious bus transactions from the host may occur. To protect the RTC internal regis- ters from corruption, all inputs are automatically locked out. The lockout condition is asserted when VCC is lower than VCCON. See section 19-8 on page 136. 6.2.14 Power-Up Detection When system power is restored after a power failure or power-off state (VCC=0), the lockout condition continues for a delay of 62 ms (minimum) to 125 ms (maximum) after the RTC switches from battery to system power. The lockout condition is switched off immediately in the fol- lowing situations: • If the Divider Chain Control bits, DV0-2, (bits 6-4 in the CRA Register) specify a normal operation mode (01X or 100), all input signals are enabled immediately upon de- tection of system voltage above VCCON. • When battery voltage is below V BATDCT and HMR is 1, all input signals are enabled immediately upon detection of system voltage above VCCON. This also initializes registers at offsets 00h through 0Dh. • If bit 7 (VRT) of the CRD Register is 0, all input signals are enabled immediately upon detection of system volt- age above VCCON. 6.2.15 Oscillator Activity The RTC oscillator is active if: q VCC power supply is higher than VCCON, independent of the battery voltage, VBAT q VBAT power supply is higher than VBATMIN, regardless if VCC is present or not. The RTC oscillator is disabled if: q During power-down (VBAT only), the battery voltage drops below VBATMIN (see Table 19-8. "Voltage Thresholds" on page 136 for the value). When this oc- curs, the oscillator may be disabled and its functional- ity cannot be guaranteed. q Software wrote 00X to DV2-0 bits of the CRA Register and VCC is removed (see Section 6.3.1 on page 69). This disables the oscillator and decreases the power consumption from the battery connected to the VBAT pin. When disabling the oscillator, the CMOS RAM is not affected as long as the battery is present at a cor- rect voltage level. Note: Since the clock multiplier uses the RTC oscillator as a reference clock, disabling the RTC oscillator will interfere with the clock multiplier functionality. See also Section 7.2 on page 76. If the RTC oscillator becomes inactive, the following fea- tures will be dysfunctional/disabled: q Timekeeping q Periodic interrupt q Alarm q APC 6.2.16 Interrupt Handling The RTC has a single Interrupt Request line, IRQ8, which handles the following three interrupt conditions: q Periodic interrupt q Alarm interrupt q Update-Ended interrupt. The interrupts are generated (IRQ8 is driven low) if the re- spective enable bits in the CRB Register are set prior to an interrupt event occurrence. See also section 5.10 "HOST INTERRUPTS" on page 52, and section 5.14.14 "IRQ En- able Register (IRQE)" on page 63. Reading the CRC Register clears all interrupt flags. Thus, when multiple interrupts are enabled, the interrupt service routine should first read and store the CRC Register, and then deal with all pending interrupts by referring to this stored status. If an interrupt is not serviced before a second occurrence of the same interrupt condition, the second interrupt event is lost. Figure 6-8 illustrates the interrupt timing in the RTC. Figure 6-8. Interrupt/Status Timing 6.2.17 Battery-Backed Register Banks and RAM The RTC and APC module has three battery-backed regis- ter banks: q Bank 0 - General Purpose Register Bank for battery- backed storage q Bank 1 - RTC Register Bank q Bank 2 - APC Register Bank Battery backup power assures information retention during system power-down. The memory maps and register content for each of the three banks is illustrated in Section 6.7 on page 74. The lower 64-byte locations of the three banks are shared. The first 14 bytes are used for time and alarm storage and as control registers. The next 50 bytes are used for general purpose memory. Flags (and IRQ) are reset at the conclusion of CRC read or by reset. A = Update In Progress (UIP) bit high before update occurs = 244 µs B = Periodic interrupt to update = Period (periodic int) / 2 + 244 µs C = Update to Alarm Interrupt = 30.5 µs P = Period is programmed by RS3-0 of CRA. UIP bit UF bit PF bit AF bit A C of CRA of CRC of CRC of CRC P/2 P/2 244 µs 30.5 µs B P |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
