PC87570-ICCSLASHVUL datasheet(10/168 Pages) NSC

10 / 168 page

Table of Contents

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12.3.3

General PS/2 Interface Operation ............................................................................... 91

12.3.4

Transmit Mode .............................................................................................................93

12.4

SHIFT MECHANISM DISABLED ............................................................................................... 94

12.4.1

Clock Signal Control .................................................................................................... 94

12.4.2

Data Signal Control ..................................................................................................... 94

12.4.3

Interrupt Generation .................................................................................................... 94

12.5

PS/2 INTERFACE REGISTERS ................................................................................................ 95

12.5.1

PS/2 Data Register (PSDAT) ...................................................................................... 95

12.5.2

PS/2 Status Register (PSTAT) .................................................................................... 95

12.5.3

PS/2 Control Register (PSCON) .................................................................................. 95

12.5.4

PS/2 Output Signal Register (PSOSIG) ...................................................................... 96

12.5.5

PS/2 Input Signal Register (PSISIG) ........................................................................... 96

12.5.6

PS/2 Interrupt Enable Register (PSIEN) ...................................................................... 96

13.0

ACCESS.bus (ACB) Interface

13.1

FEATURES ................................................................................................................................ 98

13.2

ACB PROTOCOL OVERVIEW .................................................................................................. 98

13.2.1

ACB Interface .............................................................................................................. 98

13.2.2

Data Transactions ....................................................................................................... 98

13.2.3

Start and Stop .............................................................................................................. 98

13.2.4

Acknowledge Cycle ..................................................................................................... 98

13.2.5

“Acknowledge after every byte” Rule ........................................................................... 99

13.2.6

Addressing Transfer Formats .................................................................................... 100

13.2.7

Arbitration on the Bus ................................................................................................ 100

13.3

FUNCTIONAL DESCRIPTION ................................................................................................ 100

13.3.1

Master Mode .............................................................................................................. 100

13.3.2

Slave Mode ................................................................................................................ 101

13.3.3

Power-Down .............................................................................................................. 102

13.3.4

SDA and SCL Pin Configuration ................................................................................ 102

13.3.5

ACB Clock Frequency Configuration ......................................................................... 102

13.4

ACB REGISTERS .................................................................................................................... 102

13.4.1

ACB Serial Data Register (ACBSDA) ........................................................................ 102

13.4.2

ACB Status Register (ACBST) .................................................................................. 102

13.4.3

ACB Control Status Register (ACBCST) ................................................................... 103

13.4.4

ACB Control Register 1 (ACBCTL) ............................................................................ 104

13.4.5

ACB Own Address Register (ACBADDR) ................................................................. 104

13.4.6

ACB Control Register 2 (ACBCTL2) .......................................................................... 104

13.5

USAGE HINTS ........................................................................................................................ 105

14.0

Multi-Function 16-Bit Timer (MFT16)

14.1

FEATURES .............................................................................................................................. 106

14.2

FUNCTIONAL DESCRIPTION ................................................................................................ 106

14.3

CLOCK SOURCE UNIT ........................................................................................................... 107

14.3.1

Prescaler ................................................................................................................... 107

14.3.2

External Event Clock ................................................................................................. 107

14.3.3

Pulse Accumulate Mode ............................................................................................ 107

PC87570-ICC/VUL 数据表(PDF) 10 Page - National Semiconductor (TI)

PC87570-ICC/VUL 数据表(HTML) 10 Page - National Semiconductor (TI)

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