PC87570-ICCSLASHVUL datasheet(69/168 Pages) NSC

69 / 168 page

Real-Time Clock (RTC) and Advanced Power Control (APC)

www.national.com

The upper 64 bytes of bank addresses are utilized as fol-

lows:

Bank 0 supplies an additional 64 bytes of memory-

backed RAM.

Bank 1 uses the upper 64 bytes for functions related

to RTC activity.

Bank 2 uses the upper 64 bytes for functions related

to APC activity.

Reserved registers and bits should be written using a read-

modify-write method.

The CRA Register selects the active bank according to the

value of bits 6-4 (DV0-2). See Table 6-4.

All register locations are accessed by the RTC Index and

Data Registers (at base address and base address+1). The

Index Register points to the register location being access-

ed, and the Data Register contains the data to be trans-

ferred to or from the location.

In addition to these register banks, an additional 128 bytes

of battery-backed RAM (also called upper RAM) may be ac-

cessed via two levels of addressing, as follows:

The ﬁrst level is the RTC Index and Data registers.

The second level consists of the upper RAM Address

upper RAM Data Register at second level offset 53h of

Bank 1.

There are several ways to lock access to register banks and

RAM. For details, see Section 6.6.4 on page 73.

6.3

RTC REGISTERS

The RTC registers can be accessed at any time during nor-

mal operation mode; i.e.,when VCC is within the recom-

mended operation range. This access is disabled during

battery-backed operation. The write operation to these reg-

isters is also disabled if bit 7 of the CRD Register is 0 (see

Section 6.3.4 on page 71).

Note: Before attempting to perform any start-up proce-

dures, make sure to read about bit 7 (VRT) of the

CRD Register (Section 6.3.4 on page 71).

See Section 6.7 on page 74 for a detailed description of the

memory map for the RTC registers.

This section describes the four RTC Control Registers that

control basic RTC functionality (see Table 6-2). These reg-

isters are shared by all banks.

Table 6-2. RTC Control Registers

Additional configuration registers are located at Table 5-2.

"HBI Registers Accessed by CR16A" on page 54 and Table

5-4. "HBI Registers Accessed by Host" on page 61.

6.3.1

RTC Control Register A (CRA)

This register controls bank selection, among other func-

tions.

Note: This register can not be written before reading bit 7

of the CRD Register.

Bits 3-0 - Periodic Interrupt Rate Select (RS3-0)

These read/write bits select one of fifteen output taps

from the clock divider chain to control the rate of the peri-

odic interrupt. See Table 6-3 and Figure 6-3 on page 66.

These bits are reset at power-up reset only.

Table 6-3. Periodic Interrupt Rate Encoding

Bits 6-4 - Divider Chain Control (DV2-0)l

These read/write bits control the configuration of the di-

vider chain for timing generation and register banks se-

lection. See Table 6-4.

These bits are reset at power-up reset only.

Offset Mnemonic

0Ah

CRA

RTC Control Register A

0Bh

CRB

RTC Control Register B

0Ch

CRC

RTC Control Register C

0Dh

CRD

RTC Control Register D

76543210

UIP

DV2

DV1

DV0

RS3

RS2

RS1

RS0

3 2 1 0

Periodic Interrupt

Rate (ms)

Divider

Chain

Output

0 0 0 0

No interrupts

0 0 0 1

3.906250

0 0 1 0

7.812500

0 0 1 1

0.122070

0 1 0 0

0.244141

0 1 0 1

0.488281

0 1 1 0

0.976562

0 1 1 1

1.953125

1 0 0 0

3.906250

1 0 0 1

7.812500

1 0 1 0

15.625000

1 0 1 1

31.250000

1 1 0 0

62.500000

1 1 0 1

125.000000

1 1 1 0

250.000000

1 1 1 1

500.000000

PC87570-ICC/VUL 数据表(PDF) 69 Page - National Semiconductor (TI)

PC87570-ICC/VUL 数据表(HTML) 69 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载