PC87570-ICCSLASHVUL datasheet(49/168 Pages) NSC

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Host Bus Interface (HBI)

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5.2

HOST ACCESS TO SHARED MEMORY DEVICE

The PC87570 allows the host system BIOS and the CR16A

firmware to share the same physical memory device. Typi-

cally, this memory is a Flash device to allow field upgrade

of both programs.

5.2.1

Enabling Shared Memory Mode

The host interface to the shared memory device is enabled

via the Shared BIOS Memory (SHBM) strap pin, on power-

up reset:

When SHBM is low (0), shared memory is enabled.

This is the default selected by the on-chip pull-down.

When SHBM is high (1), the memory device is not

shared. In this case, nine additional I/O port signals

are available instead HMEMR, HMEMW, HMEMCS,

HA16-18 and A16-18 (see Section 2.5 for alternate

function settings).

Setting SHBM is described in Section 2.7.

5.2.2

Memory Device Interface

The memory device is connected directly to the PC87570.

The BIU arbitrates the usage of the memory. Different types

of memory devices with different access times can be used

by programming the BIU configuration registers (see Chap-

ter 3).

5.2.3

Host Access to Shared Memory

The host can access the memory through the HBI, core bus

and BIU. The PC87570 generates the memory control sig-

nals and bridges the address and data from the host bus to

the memory bus. See “Block Diagram” on page 1.

The shared memory is accessed using host bus memory

cycles. To read from the memory, the host asserts the

HMEMR and HMEMCS signals. To write to the memory, it

asserts the HMEMW and HMEMCS signals. The HBI iden-

tifies these commands, and requests control over the core

bus to perform these read and write operations. During host

access to the shared memory, the ISA bus cycle is extend-

ed using HIOCHRDY signal.

Host access to the shared memory can be completed only

when the PC87570 is out of reset, in Active mode, and

SHMEN and SHOFF in the MCFG Register are set (1). On

power-up reset, the Host Reset Mode Select (HRMS) strap

pin determines the handling of accesses that cannot be

completed, as follows (see also how to set HRMS in Section

2.4):

When HRMS is low (0) and access to the shared

memory is enabled (SHBM=0), an access by the host

to shared memory which the PC87570 cannot com-

plete is extended by HIOCHRDY until the PC87570

completes the transaction (i.e., after reset, in Active

mode, with SHMEN and SHOFF set).

When HRMS is high (1) and access to the shared

memory is enabled (SHBM=0), an access by the host

to shared memory which the PC87570 cannot com-

plete causes the PC87570 to generate an active low

host reset signal (HRSTO=0). Reset ends when both

HMEMR and HMEMW are inactive (high) and the

PC87570 completes a host access. In this case, the

PC87570 does not perform the bus cycle to memory.

Host Bus Memory Cycles

The host bus cycles are detailed in Section 19.5.2.

The host data bus is 8 bits wide. When the PC87570 uses

a 16-bit wide Flash memory, the 8-bit read or write opera-

tion is directed to the lower (0 through 7) or higher (8

through 15) bits of the memory data bus, according to the

host least significant address bit (HA0).

Host memory write operations are performed to a buffer in

the PC87570. The actual write to the shared memory is ex-

ecuted only after the host write is completed. If the

PC87570 is reset before this write is completed, data may

not be written to memory.

5.3

CORE ACCESS TO RTC/APC

The CR16A can access the on-chip RTC/APC through a

pair of registers, RTCCA and RTCCD. These two registers

are the same Index and Data registers when accessed from

the ISA bus at addresses 0070h and 0071h. See Section

5.12.1 for details.

5.3.1

Host and CR16A Arbitration over RTC/APC

Due to the indirect nature of RTC/APC access, the host

software and the PC87570 firmware cannot access the

RTC simultaneously. The host software and PC87570 firm-

ware must communicate to prevent conflicts in RTC register

usage. Without this communication, the host might set an

index which the PC87570 changes before the host can ac-

cess the RTC data. Also, this prevents interruption of cer-

tain RTC operations that require a sequence of bus

operations. LKRTCHA in the CTS1 Register controls ac-

cess to the RTC/APC, as follows:

• When LKRTCHA is cleared, access to the RTC regis-

ters by the host is enabled, while CR16A access to them

is blocked (i.e., write operations are ignored and read

operations return an unpredictable value).

• When LKRTCHA is set, CR16A access to the RTC reg-

isters is enabled, while any access to them by the host

is blocked, (i.e., write operations are ignored and read

operations return an unpredictable value).

The PC87570 firmware can access the RTC only while the

PC87570 is in Active mode. To do so, it should use the fol-

lowing sequence:

1. After arbitrating the use of the RTC with the host, set

LKRTCHA.

2. Read and save the RTC index (0070h) and the RTC

bank selection.

3. To access locked memory locations in the RTC, set

RTCMR in the CST1 Register to clear the RTC lock bits.

4. Access the RTC CMOS-RAM and its registers. To pre-

vent conflicts with the host software, the firmware

should not change any of the RTC volatile registers.

5. After RTC access has been completed:

— Relock RTC memory if it was unlocked

— Restore the RTC bank selection and the index value

6. Clear LKRTCHA to allow the host to access the RTC.

5.4

USAGE HINTS

5.4.1

Shared Memory

When using shared memory, the host should copy the BIOS

program to RAM during the boot process. This prevents

contention between the BIOS and PC87570 firmware.

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