PC87570-ICCSLASHVUL datasheet(96/168 Pages) NSC

96 / 168 page

PS/2 Interface

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Bit 7 - Weak Pull-Up Enable (WPUEN)

When set, this bit enables the internal pull up of the out-

put buffer. In such case, the pull up is active when the

buffer does not drive the signal to low level. When

cleared, the pull-up is disabled. In this state, the system

must ensure the PS/2 interface signals are not floating

to enable proper PS/2 operation.

12.5.4

PS/2 Output Signal Register (PSOSIG)

The PSOSIG Register is a byte wide, read/write register. It

allows setting the value of the PS/2 port signals. When the

shift mechanism is enabled, the clock control bits in this reg-

ister define the active channel(s). On reset, the non-re-

served bits of PSOSIG are set to 07h.

Bit 0 - Write Data Signal Channel 1 (WDAT1)

Controls the data output to channel 1 data signal

(PSDAT1).

When the shift mechanism is disabled (PSCON.EN=0),

the data in WDAT1 is output to PSDAT1 signal. If

WDAT1 is cleared (0), the output buffer data is 0 (i.e.,

PSDAT1 is forced low). If WDAT1 is set (1), the output

buffer data is 1 (i.e., PSDAT1 is pulled high by the inter-

nal pull-up and may be pulled low by an external de-

vice).

When the shift mechanism is enabled (EN=1), WDAT1

should be set to 1, except when the shift mechanism is

transmit mode. In this case, when in transmit-inactive

and it is intended to transmit data to channel 1, the firm-

ware should clear WDAT1 bit to force the transmit sig-

naling (low) to the PS/2 device.

WDAT1 is set by the hardware after the PC87570 de-

tected a start bit (i.e., on entering the Transmit Active

state). If a transmission is aborted before the transmit-

active state, WDAT1 should be set (1) prior to disabling

the channel.

Bit 1 - Write Data Signal Channel 2 (WDAT2)

Same as WDAT1 but for channel 2.

Bit 2 - Write Data Signal Channel 3 (WDAT3)

Same as WDAT1 but for channel 3.

Bit 3 - CLK1, Enable Channel 1

When cleared (0), forces a low (0) on the PSCLK1 pin

and disables channel 0 of the shift mechanism.

When the shift mechanism is enabled (PSCON.EN=1),

and CLK1 is set (1), channel 1 of the PS/2 ports is en-

abled.

When

the

shift

mechanism

disabled

(PSCON.EN=0) and CLK1 bit is set (1), the clock line

output buffer data is 1 (i.e., the signal is pulled high by

the pull-up if enabled, and may be pulled low by an ex-

ternal device).

Bit 4 - Enable Channel 2 (CLK2)

Same as CLK1 but for channel 2.

Bit 5 - Enable Channel 3 (CLK3)

Same as CLK1 but for channel 3.

Note:

When CLK1, CLK2 and CLK3 are all 0, this is interpreted as

a shift mechanism reset. In this case, the PSTAT Register

and the shift state machine are reset to their initial state.

12.5.5

PS/2 Input Signal Register (PSISIG)

The PSISIG Register is an 8-bit read only register. It pro-

vides the current value of the PS/2 port signals.

Bit 0 - Read Data Signal Channel 1 (RDAT1)

The current value of the channel 1 data signal

(PSDAT1).

Bit 1 - Read Data Signal Channel 2 (RDAT2)

Same as RDAT1 but for channel 2.

Bit 2 - Read Data Signal Channel 3 (RDAT3)

Same as RDAT1 but for channel 3.

Bit 3 - Read Clock Signal Channel 1 (RCLK1)

When read, returns the current value of the channel 1

clock signal (PSCLK1).

Bit 4 - RCLK2, Read Clock Signal Channel 2

Same as RCLK1 but for channel 2.

Bit 5 - RCLK3, Read Clock Signal Channel 3

Same as RCLK1 but for channel 3.

12.5.6

PS/2 Interrupt Enable Register (PSIEN)

The PSIEN Register is an 8-bit read/write register. It en-

ables/disables the various interrupts generated by the PS/2

module. Bits in the PSIEN Register may be cleared to 0 only

when interrupts are disabled, i.e., in the CR16A core, the

PSR.I or the PSR.E bits are 0 or when the corresponding in-

terrupts in the ICU are masked. Bits in the PSIEN Register

may be set to 1 at any time. On reset, non reserved bits of

PSIEN are cleared.

000

1 cycle

001

2 cycles

010

4 cycles

011

8 cycles

100

16 cycles

101

32 cycles

7 6

Res

CLK3

CLK2

CLK1 WDAT3 WDAT2 WDAT1

7 6

4321

Res

RCLK3 RCLK2 RCLK1 RDAT3 RDAT2 RDAT1

Reserved

DSMIE

EOTIE

SOTIE

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