PC87570-ICCSLASHVUL datasheet(35/168 Pages) NSC

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Bus Interface Unit (BIU)

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cifically configured as a pause between two consecutive

transactions. When more than one Tidle cycle is requested

as a pause, the Tidle cycles overlap and only one Tidle cycle

is added.

Tidle clock cycles can be inserted between two consecutive

accesses in different zones (to allow long hold times or buff-

er disable times). To do this either program SZCFGn.IPRE

and/or SZCFGn.IPST (or IOCFG.IPST). See Figure 3-7 on

page 40.

Tidle clock cycles are also added between an early write and

any read bus cycles, and between a late write and fast read

bus cycles. See Figure 3-12 on page 43.

T1 Cycle

Every bus cycle starts with T1. In this clock cycle the ad-

dress of the selected device (either external or internal) is

set on the address pins. Write bus cycles never drive data

during T1.

T2 Cycle

The read T2 bus cycles always sample the data at the end

of T2.

The write T2 bus cycles always drive data during T2. If no

Thold clock cycles follow, the data bus is put in TRI-STATE

after the T2 cycle.

T1-2 Cycle

The fast read T1-2 bus cycle is one-cycle read duration.

At the beginning of the clock cycle, the address of the se-

lected device is set on the address pins and the SELn and

RD signals are activated. At the end of the clock cycle, the

BIU samples the data.

T3 Cycle

Early write bus cycles always have the T3 clock cycle. All

other bus cycles do not have this clock cycle.

At the beginning of this clock cycle SELn (or SELIO) deac-

tivates and then WR(0-1) deactivates. The address and

data remains valid until T3 is completed. If no Thold clock cy-

cles follow, the data bus is put in TRI-STATE after the T3

cycle.

The following clock cycles are optional in a data transfer bus

cycle:

TIW (Internal Wait)

Thold

T2B (T2 burst)

TBW (Burst Wait).

TIW Cycle

Extend the basic data transfer bus cycle by adding wait

clock cycles. To do this, either program SZCFGn.WAIT (or

IOCFG.WAIT) with the required additional wait clock cycles.

Wait clock cycles generated due to SZCFGn.WAIT (or IO-

CFG.WAIT) are named TIW (internal wait). TIW cycles are

added after T1 and followed by T2 cycles. Data is always

driven during wait clock cycles of a write bus cycle.

TBW Cycle

A burst bus cycle can be extended by one wait clock cycle,

named TBW. This is done according to SZCFGn.WBR. The

address is changed in the beginning of TBW. Write bus cy-

cles do not have this clock cycle.

T2B Cycle

Data of read burst bus cycles is sampled at the end of T2B.

If TBW cycle is not configured, the address is changed in

the beginning of T2B. Write bus cycles do not have this

clock cycle.

Thold Cycle

Hold cycles are added after T2 or T2B (if there is a burst bus

cycle)

(according

SZCFGn.HOLD

IO-

CFG.HOLD); the address and data (during a write bus cy-

cle) are always valid during these cycles. The data bus is

put in TRI-STATE after the last Thold.

Special Tidle Cycle

During Tidle cycles, one of the SEL0-1 signals and the RD

signal may be activated for one clock cycle. This happens

due to special activity on the internal core bus.

To avoid contention on the memory bus, it is guaranteed

that this clock cycle is followed by a sufficient number of

Tidle cycles before the next T1 cycle is performed.

The number of Tidle cycles following is at least the number

required by the selected zone as configured in the HOLD

field of the SZCFGn Register.

3.3.2

Control Signals

A read bus cycle consisting of the basic bus cycle plus ad-

ditional clock cycles (the burst bus cycle) occurs if the bus

is burstable (SZCFGn.BRE is 1), the configured bus width

is 8 bits, and the core attempts to read a word. When the

bus is not burstable (SZCFGn.BRE is 0), the BIU issues two

separate read bus cycles. Write bus cycles are never burst-

able, and the BIU always issues two separate write bus cy-

cles.

The write bus cycles use byte write qualifiers on WR0-1

pins:

• They access an 8-bit wide memory on D0-7 data lines.

One byte is accessed on basic bus cycles. Only WR0

pin is used as the byte write qualifier.

• They access a 16-bit wide memory on D0-15 data lines.

Either one or two bytes are accessed on basic bus cy-

cles. WR0 pin is used as even byte (D0-7) write qualifier

and WR1 pin is used as odd byte (D8-15) write qualifier.

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