PC87570-ICCSLASHVUL datasheet(88/168 Pages) NSC

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General Purpose I/O (GPIO) Ports

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11.0 General Purpose I/O (GPIO) Ports

The PC87570 provides up to 76 GPIO pins. Some GPIO

signals share their pins with an alternate function (see Sec-

tion 2.5 on page 27).

11.1 FEATURES

The GPIO ports are subdivided into the following groups,

each with its own unique set of features:

Ports PA(0-6), PB(0-7), PC(0-7) and PE(0-1) are on-

chip bidirectional (I/O) ports that support GPIO alter-

nate functions and an internal weak pull-up. The fol-

lowing exceptions apply:

— PA has no PxALT register. Its alternate function is

controlled by a strap option.

— PBALT.6 is always 1, i.e., conﬁgured for its alternate

function.

— PBDIR.5 and PBDOUT.5 are set on reset, conﬁgur-

ing bit 5 to be output with data set. PBALT.5 must al-

ways be set to 0.

— Port PC is initialized on power-up and WATCHDOG

reset only. It is unchanged after Warm reset.

Ports PF(0-7), PG(0-4) and PH(0-5) are bidirectional

(I/O) ports that support GPIO alternate functions but

do not have an internal weak pull-up option.

Port PD(0-7) is on-chip input only.

Port KBSIN0-7 is an on-chip input port dedicated to

the keyboard scan with weak pull-up support.

Port KBSOUT0-15 is an on-chip output port dedicated

to the keyboard scan.

Figure 11-1 illustrates a GPIO port diagram which includes

all available features.

11.2 FUNCTIONAL DESCRIPTION

11.2.1

Output Buffer

The output buffer is a TRI-STATE buffer. The output type

(i.e., CMOS or TTL) and its driving capabilities are de-

scribed in Table 19-7 on page 135.

11.2.2

Input Buffer

The I/O port input buffer characteristics are defined in Table

19-7 on page 135.

The input buffer has an enable input. When enabled, the

buffer inputs the pin’s logic level to the on-chip modules.

When disabled, the input is blocked to prevent supply leak-

age currents.

11.2.3

Open Drain

To use the GPIO pin as an inverting open-drain output buff-

er, the software should clear the corresponding bit in the

Data Out (PxDOUT) register, and then use the direction

When the signal’s direction is set as output (1), a val-

ue of 0 is forced.

When the direction is set for input (0), the signal is in

TRI-STATE and is not forced low.

11.2.4

Weak Pull-Up

The internal weak pull-up can be used to pull-the signal high

when it is not forced low, by writing (1) to the corresponding

bit of PxWPU. Pull-up characteristics are defined in Table

19-7 on page 135.

Direction

Weak Pull-up

Data In Register

Data Out

Alt Device Data Output

Alt

Alt Device Direction

Alt Device Data Input

Data In Read

Pull-up

Weak Pull-up

Alt Function

PxAlt

(PxWPU)

(PxDIR)

(PxDOUT)

PxDIN

Alt

Figure 11-1. GPIO Port Schematic Diagram

Data Out

{

Signal

Alt

Px = Any GPI port

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