PC87570-ICCSLASHVUL datasheet(43/168 Pages) NSC

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Bus Interface Unit (BIU)

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3.3.7

I/O Expansion Bus Cycles

The I/O expansion bus cycles enables you to implement the

functionality of on-chip I/O ports (when the pins of the on-

chip I/O ports are used to support IRD or Dev environment)

and/or additional ports, using off-chip external logic.

I/O expansion bus cycles access the off-chip I/O device us-

ing the following signals:

SELIO

Address lines A0-7

The RD and WR0-1 signals may be used.

The design minimizes the off-chip logic required to imple-

ment the I/O ports. It is costly to implement a port with pins

individually configured for input or output. Implementing

ports which are input only or output only, reduces expenses.

I/O expansion bus cycle is not generated during an access

to a port register when:

Any port pin is available on-chip

All port pins are inputs, and the port is being written.

I/O Expansion Read/Write Bus Cycle

These cycles are always preceded by a Tidle clock cycle.

See Figure 3-13. The I/O zone is not burstable.

CLK

A0-18

SELx

SELy

WR0-1

D0-15

Fast

Late Write

Fast

TIdle

T1-2

Read

TIdle

Out

BST0-2

≠ y)

≠ x)

Idle

Cycle

Figure 3-12. Fast Read Bus Cycle

CLK

A0-18

SELIO

WR0-1

D0-15

Read

Write

TIdle

Out

BST0-2

Figure 3-13. I/O Expansion Bus Cycles (BCFG.EWR = 1)

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