PC87570-ICCSLASHVUL datasheet(90/168 Pages) NSC

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PS/2 Interface

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12.0 PS/2 Interface

Industry-standard PC-AT-compatible keyboards use a two-

wire, bidirectional TTL interface for data transmission. Sev-

eral vendors also supply PS/2 mouse products and other

pointing devices that employ the same type of interface.

The PC87570 provides three PS/2 data transfer channels.

Each channel has two quasi-bidirectional signals that serve

as direct interfaces to an external keyboard, mouse or any

other PS/2-compatible pointing device. Since the three

channels are identical, the connector ports are interchange-

able.

12.1 FEATURES

Three PS/2 channels

Enable/Disable for each of the three channels

Automatic hardware shift mechanism

Hardware support for PS/2 auxiliary device protocol

Processor interrupts at the beginning and end of data

transfer

Optional software-based PS/2 implementation

12.2 FUNCTIONAL DESCRIPTION

12.2.1

Configuration

The PS/2 interface includes six external signals (PSCLK1,

PSDAT1, PSCLK2, PSDAT2, PSCLK3 and PSDAT3) and

six registers. Channels 1 and 2 always have assigned pins.

A special configuration, shown in Figure 12-1, is required to

also make channel 3 available. See Section 12.5 for register

details.

12.2.2

Shift Mechanism

The shift mechanism is a proprietary hardware accelerator

that ofﬂoads bit level handling of data transfer from the firm-

ware to hardware. It can be enabled to operate in Receive

or Transmit mode, or disabled. Different states in each

mode define the progress of data transfer.

Shift Mechanism Enabled

PS/2 devices’ firmware is significantly simplified when the

shift mechanism is enabled. Using the shift mechanism to

receive or transmit PS/2 data reduces code overhead and

performance requirements from the CompactRISC CR16A

core, and improves the overall interrupt latency of the

PC87570. The shift mechanism includes an 8-bit shift reg-

ister, a state machine and control logic that handle both in-

coming and outgoing data.

Shift Mechanism Disabled

Previous generation keyboard controllers executed the

PS/2 device interface by toggling and monitoring the PS/2

device interface signals via firmware. The PC87570 also

supports this bit toggling mode with polling or interrupt-driv-

en, clock edge detection by disabling the shift mechanism.

The hardware is designed to meet the PS/2 device interface

as defined in “Keyboard and Auxiliary Device Controller

(Types 1 and 2)” - August 1988.

12.2.3

Quasi-Bidirectional Drivers

The quasi-bidirectional drivers have an open drain output

(Q2), an internal pull-up (Q3) and a low impedance pull-

up(Q1). Q2 pulls the signal low whenever the output buffer

data is “0”. The weak pull-up (Q3) is active whenever the

output buffer data is “1” and PSCON.WPUEN is set (1). The

low impedance pull-up is active whenever the PC87570

changes the output data buffer from “0” to “1”, thereby re-

ducing the low to high transition time. The low impedance

pull-up active duration is determined by PSCON.HDRV

field. A schematic description of this output driver appears

in Figure 12-3.

Channel 3

Channel 1

Channel 2

Shift Mechanism

EN1

PSCLK1

PSDAT1

DATO1

DATI1

CLKO1

CLKI1

EN2

DATO2

DATI2

CLKO2

CLKI2

EN3

DATO3

DATI3

CLKO3

CLKI3

CLK1

WDAT1

RCLK1

RDAT1

ENSM

PS/2 I/F

Registers

Figure 12-1. PS/2 Interface Functional Diagram

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