PC87570-ICCSLASHVUL datasheet(95/168 Pages) NSC

95 / 168 page

PS/2 Interface

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The ICU should be programmed to detect a falling edge on

each of the clock signals. Disabling a channel by writing 0

to the clock control signals (CLK1, CLK2 or CLK3) may

cause a falling edge on a clock signal. When such an inter-

rupt is not desired, clear (0) the clock control bit and then

the pending bit in the ICU. This should be done while inter-

rupts are disabled. For more details about the ICU, see Sec-

tion 9.3 on page 82.

12.5 PS/2 INTERFACE REGISTERS

12.5.1

PS/2 Data Register (PSDAT)

The PSDAT Register is a byte wide, read/write register. In

Receive mode, PSDAT holds the data received in the last

message from the PS/2 device. In Transmit mode, the data

to be shifted out is written to this register. When the PS/2 i/f

is reset, the contents of this register become invalid.

On reset, the PS/2 interface is set to Receive mode. In this

mode, the PSDAT should be read only when the

PSTAT.EOT bit is set (1).

Setting the transmit enable bit in the PSCON register to 1

(PSCON.XMT = 1) puts the PS/2 interface in Transmit

mode. The PSDAT should be written only when in Transmit

mode, and all three channel enable bits PSOSIG.CLKi (i in

the range of 1 through 3) are cleared (0).

Bits 7-0 - Data

Contains the data received in the last message (or that

is transmitted in the following transmission). Bit 0 is the

first bit to be shifted (LSB).

12.5.2

PS/2 Status Register (PSTAT)

The PSTAT Register is a byte wide, read only register. It

contains the status information on the data transfer on the

PS/2 ports. All non-reserved bits of PSTAT are cleared (0)

on reset, when the CLK1, CLK2 and CLK3 in PSOSIG are

cleared and when PSCON.EN is cleared. Reading PSTAT

does not clear any of its bits.

Bit 0 - Start of Transaction (SOT)

Indicates that a start bit was detected. ACH field indi-

cates which of the channels it was detected on.

Bit 1 - End of Transaction (EOT)

Indicates that a PS/2 data transfer was completed - a

stop bit was detected at the receive mode or a line con-

trol bit at transmit mode.

Bit 2 - Parity Error (PERR)

Indicates a parity error detection in the last transfer.

Bits 5-3 - Active Channel (ACH)

Defines which of the PS/2 channels is currently active

(i.e., a start bit was detected). In case more than one

channel become active simultaneously, only the one

with the highest priority (lowest number) is flagged.

000 = None of the channels is active

001 = Channel 1

010 = Channel 2

100 = Channel 3

Bit 6 - Receive Frame Error (RFERR)

Indicates that the stop bit in a received frame was de-

tected low instead of high.

12.5.3

PS/2 Control Register (PSCON)

The PSCON Register is an 8-bit read/write register. It con-

trols the operation of the PS/2 interface by enabling it and

controlling the data transfer direction. On reset, PSCON is

set to 00h.

Bit 0 - Shift Mechanism Enable (EN)

When set (1), the hardware shift mechanism is enabled.

The enabled channels are controlled by PSOSIG and

the transmit/receive mode is controlled by the XMT bit.

When cleared (0), the mechanism is disabled and the

software may control and monitor the PS/2 signals using

PSOSIG and PSISIG registers.

Bit 1 - Transmit Enable (XMT)

When set (1), causes the PS/2 interface to enter the

transmit mode. When cleared (0), it is in the receive

mode.

Bits 3-2 - High Drive (HDRV)

The HDRV field defines the quasi-bidirectional buffers’

behavior on the transition from low to high. HDRV de-

fines the period of time for which the output is pulled

high with a low impedance drive (when the PC87570

changes the output level from low to high). This period

is a function of the PC87570 clock as follows:

Bits 6-4 - Input Debounce (IDB)

This IDB field defines the number of PC87570 clock cy-

cles during which the clock input is expected to be sta-

ble before the shift mechanism identifies its new value.

This protects the shift mechanism from false edge de-

tections. The number of PC87570 clock cycles for which

the input should be stable before an edge is detected, is

as follows:

Data

Res

RFERR

ACH

PERR

EOT

SOT

WPUEN

IDB

HDRV

XMT

0 0

Disabled

0 1

low impedance drive for one clock cycle

1 0

low impedance drive for two clock cycle

1 1

low impedance drive for three clock cycle

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