PC87570-ICCSLASHVUL datasheet(98/168 Pages) NSC

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ACCESS.bus (ACB) Interface

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13.0 ACCESS.bus (ACB) Interface

The ACB interface is a two wire serial interface compatible

with the ACCESS.bus physical layer. It is also compatible

with Intel’s SMBus and Philips’ I2C bus. The module can be

configured as a bus master or slave, and can maintain bidi-

rectional communications with both multiple master and

slave devices.

13.1 FEATURES

ACCESS.bus, SMBus and I2C compliant

ACCESS.bus master and slave

Supports polling and interrupt controlled operation

Generates a wake-up signal on detection of a Start

Condition, while in power-down mode

Optional internal pull-up on SDA and SCL pins

13.2 ACB PROTOCOL OVERVIEW

The ACB interface provides full support for a two-wire AC-

CESS.bus, synchronous serial interface. It permits easy in-

terfacing to a wide range of low-cost memories and I/O

devices, including: EEPROMs, SRAMs, timers, A/D con-

verters, D/A converters, clock chips and peripheral drivers.

13.2.1

ACB Interface

The ACCESS.bus protocol uses a two-wire interface for bi-

directional communications between the ICs connected to

the bus. The two interface lines are the Serial Data Line

(SDL), and the Serial Clock Line (SCL). These lines should

be connected to a positive supply, via a pull-up resistor, and

remain HIGH even when the bus is idle.

The ACCESS.bus protocol supports multiple master and

slave transmitters and receivers. Each IC has a unique ad-

dress and can operate as a transmitter or a receiver

(though, some peripherals are only receivers).

During data transactions, the master device initiates the

transaction, generates the clock signal and terminates the

transaction. For example, when the ACB initiates a data

transaction with an attached ACCESS.bus compliant pe-

ripheral, the ACB becomes the master. When the peripheral

responds and transmits data to the ACB, their master/slave

(data transaction initiator and clock generator) relationship

is unchanged, even though their transmitter/receiver func-

tions are reversed.

13.2.2

Data Transactions

One data bit is transferred during each clock pulse. Data is

sampled during the high state of the serial clock (SCL).

Consequently, throughout the clock’s high period the data

should remain stable (see Figure 13-1). Any changes on the

SDA line during the high state of the SCL and in the middle

of a transaction, aborts the current transaction. New data

should be sent during the low SCL state. This protocol per-

mits a single data line to transfer both command/control in-

formation and data using the synchronous serial clock.

Each data transaction is composed of a Start Condition, a

number of byte transfers (set by the software) and a Stop

Condition to terminate the transaction. Each byte is trans-

ferred with the most significant bit first, and after each byte

(8 bits), an Acknowledge signal must follow. The following

sections provide further details of this process.

At each clock cycle, the slave can stall the master while it

handles the previous data, or prepares new data. This can

be done, for each bit transferred, or on a byte boundary, by

the slave holding SCL low to extend the clock-low period.

Typically, slaves extend the first clock cycle of a transfer if

a byte read has not yet been stored, or if the next byte to be

transmitted is not yet ready. Some microcontrollers, with

limited hardware support for ACCESS.bus, extend the ac-

cess after each bit, thus allowing the software time to han-

dle this bit.

13.2.3

Start and Stop

The ACCESS.bus master generates Start and Stop Condi-

tions (control codes). After a Start Condition is generated

the bus is considered busy and it retains this status till a cer-

tain time after a Stop Condition is generated. A high-to-low

transition of the data line (SDA) while the clock (SCL) is

high, indicates a Start Condition. A low-to-high transition of

the SDA line while the SCL is high indicates a Stop Condi-

tion (Figure 13-2).

In addition to the first Start Condition, a repeated Start Con-

dition can be generated in the middle of a transaction. This

allows another device to be accessed, or a change in the di-

rection of the data transfer.

13.2.4

Acknowledge Cycle

The Acknowledge Cycle consists of two signals: the ac-

knowledge clock pulse the master sends with each byte

transferred, and the acknowledge signal sent by the receiv-

ing device (Figure 13-3).

The master generates the acknowledge clock pulse on the

ninth clock pulse of the byte transfer. The transmitter releas-

es the SDA line (permits it to go high) to allow the receiver

to send the acknowledge signal.The receiver must pull

SDA

SCL

Data Line

Stable:

Data Valid

Change

of Data

Allowed

Figure 13-1. Bit Transfer

SDA

SCL

Start

Condition

Stop

Condition

Figure 13-2. Start and Stop Conditions

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