PC87570-ICCSLASHVUL datasheet(81/168 Pages) NSC

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Interrupt Control Unit (ICU)

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9.0

Interrupt Control Unit (ICU)

The ICU is a sixteen-channel interrupt control unit. It inter-

faces between the internal/external interrupt requests and

the CompactRISC CR16A core. It generates both maskable

and non-maskable interrupts.

9.1

FEATURES

Non-Maskable Interrupts (NMI)

Handles one NMI source

Generates an NMI to the core.

Maskable Interrupts

16 interrupt sources

Supports CR16A vectored interrupts

Fixed priority among interrupt sources

Individual enable/disable of each interrupt source

Supports polling by an interrupt pending register

Programmable triggering mode and polarity.

9.2

FUNCTIONAL DESCRIPTION

9.2.1

NMI

The ICU receives an NMI signal from an external source

through the PFAIL pin. Despite its name, this pin may be

used as a general purpose NMI request source. The signal

originating from this pin is fed through the ICU into the

core’s NMI input.

When NMI processing begins, the core performs an inter-

rupt acknowledge core-bus cycle. The address associated

with this core bus cycle (0FF00h) is found within the internal

address space and may be monitored in the development

system (see Sections 18.4 on page 130 and 3.4 on page

44).

After reset, PFAIL must be inactive until the firmware initial-

izes the interrupt table and the interrupt base.

To generate a trap, a falling edge on the PFAIL pin is asyn-

chronously detected. When this occurs, PFAIL (bit 0) in the

NMISTAT Register is set to 1 and an NMI request to the

core is issued.

The PFAIL pin has Schmidt trigger characteristics and an

internal synchronization circuit; no external synchronizing

circuit is needed.

9.2.2

Maskable Interrupts

The ICU receives interrupt signals from internal and exter-

nal sources, and generates a vectored interrupt to the

CR16A when required. Priority among the interrupt sources

is fixed (see the Priority column in Table 9-2). Each interrupt

source can be individually enabled or disabled. Pending in-

terrupts, enabled or disabled, can be polled using the inter-

rupt pending register.

When processing of a maskable interrupt begins, the core

performs an interrupt acknowledge core-bus cycle. The ad-

dress associated with this core bus cycle, 0FE00h, is found

within the internal address space and may be monitored in

the development system (see “Monitoring Activity During

Development” on page 2-172). IVCT is read in the interrupt

acknowledge cycle and its data is the interrupt vector num-

ber.

9.2.3

Edge/Level and Polarity Selection

The ICU triggering mode and polarity of each interrupt

source (individually) are both programmed via the Interrupt

Edge/Level Trigger Register (IELTG) and the Interrupt Trig-

ger Polarity Register (ITRPL).

Both the polarity and the triggering mode of the interrupt sig-

nals that are generated on-chip are fixed. It is the firmware’s

task to program the respective bits in IELTG and ITRPL as

required.

Program the respective bits of IELTG and ITRPL Register

s, to control the ICU mode and polarity, as follows:

Table 9-1. Interrupt Type Programming

9.2.4

Pending Interrupts

Edge-triggered interrupts are latched by the Interrupt Pend-

ing Register (IPEND). A pending edge-triggered interrupt is

cleared by writing the required value to the Edge Interrupt

Clear Register (IECLR). A pending level-triggered interrupt

is cleared only when the interrupt source is not active.

The Interrupt Vector Register (IVCT) holds the pending In-

terrupt vector of the non-masked interrupt with the highest

priority (highest number). IVCT is automatically read during

the interrupt acknowledge cycle. Interrupt vector numbers

are always positive, in the range 20h to 2Fh.

Pending interrupt bits and interrupt mask bits (i.e., Interrupt

Enable and Mask, IENAM, and IPEND Register bits), may

be cleared to 0 only when interrupts are disabled, i.e., the

PSR.I and/or PSR.E bits are 0. IENAM bits may be set at

any time.

9.2.5

External Interrupt Inputs

The external interrupt inputs are asynchronous. They are

recognized by the PC87570 during clock cycles in which the

input setup and hold time requirements are satisfied. To use

an external interrupt that is shared with an I/O port, config-

ure the I/O port to its alternate function (see Table 2-5 on

page 27).

9.2.6

Interrupt Assignment

Table 9-2 shows the mapping of the ICU Maskable inter-

rupts to different functions. The interrupt mapping is fixed.

When interrupts from internal sources are used, the firm-

ware should program their types (edge/level and polarity)

according to the “type” field in Table 9-2. For Internal inter-

rupts, refer to the module which is the interrupt source for

information on mask bits and on the clear mechanism of lev-

el interrupts.

IELTG.i

ITRPL.i

Mode

Low Level

High Level

Falling Edge

Rising Edge

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