PC87570-ICCSLASHVUL datasheet(83/168 Pages) NSC

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Interrupt Control Unit (ICU)

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Bit 1 - PFAIL Pin Value (PIN)

Holds the current (non-inverted) PFAIL pin value. PIN is

a read only bit; data written to it is ignored.

9.3.3

Interrupt Vector Register (IVCT)

The IVCT Register is a byte-wide, read only register. It holds

the vector number of the interrupt vector. IVCT is set to 20h

upon reset.

Bits 3-0 -Interrupt Vector (INTVECT)

This field contains the encoded value of the highest pri-

ority, enabled, pending interrupt. It is valid during an in-

terrupt acknowledge core bus cycle in which IVCT is

read. It may contain invalid data when INTVECT is up-

dated.

9.3.4

Interrupt Enable and Mask Register (IENAM)

The IENAM Register is a word-wide, read/write register.

Each of the bits of IENAM enables the respective interrupt

input of the ICU (i.e., bits 0 through 15 correspond to INT0

through INT15, respectively). IENAM is cleared on reset.

IENAM bits can be cleared only when interrupts are dis-

abled. Each bit is encoded as follows:

0: Interrupt disabled

1: Interrupt enabled

9.3.5

Interrupt Pending Register (IPEND)

The IPEND Register is a word-wide, read only register. It in-

dicates which interrupts are pending, regardless of the con-

tents of the corresponding IENAM bit. Bits 0 through 15 of

IPEND correspond to interrupts INT0 through INT15, re-

spectively. After reset, IPEND bits are undefined. Each bit

is encoded as follows:

0: Interrupt not pending

1: Interrupt pending

9.3.6

Edge Interrupt Clear Register (IECLR)

The IECLR Register is a word-wide, write only register used

to clear pending, edge-triggered interrupts. Writing to the bit

positions of level-triggered interrupts has no effect. Bits 0

through 15 of IECLR correspond to INT0 through INT15, re-

spectively. Each bit is encoded as follows:

0: No effect

1: Clear the corresponding pending interrupt

9.3.7

Edge/Level Trigger Configuration Register (IELTG)

The IELTG Register is a word-wide, read/write register.

Each bit defines the way that the corresponding interrupt re-

quest is triggered, either edge-sensitive or level-sensitive.

Bits 0 through 15 of IETLG correspond to INT0 through

INT15, respectively. Each of IELTG bits is encoded as fol-

lows:

0: Level-sensitive

1: Edge-sensitive

9.3.8

Trigger Polarity Configuration Register (ITRPL)

The ITRPL Register is a word-wide, read/write register. It

controls the triggering polarity of the ICU. Bits 0 through 15

of ITRPL correspond to INT0 through INT15, respectively.

Each of ITRPL bits is encoded as follows:

Level-sensitive trigger type:

0: Low level

1: High level

Edge-sensitive trigger type:

0: Falling edge

1: Rising edge

9.4

USAGE HINTS

9.4.1

Initializing

1. Initialize the INTBASE register of the core.

2. Program the interrupts’ triggering mode and polarity.

3. Prepare the interrupt routines of the interrupts used.

4. Clear pending edge-interrupts used.

5. Set the relevant bits of IENAM.

6. Enable the core interrupt.

9.4.2

Clearing

To prevent spurious interrupts (CR16A detection of inter-

rupts not reflected by IVCT), perform the following opera-

tions only when interrupts are disabled:

1. Clearing an interrupt request

2. Changing the triggering mode or polarity

3. Clearing IENAM bits. These bits should be cleared while

the CR16A interrupts are disabled (i.e., PSR.I bit and/or

PSR.E bit is cleared).

9.4.3

Nesting

You can use the IENAM Register in interrupt handlers to al-

low nesting of interrupts. When the core acknowledges an

interrupt, it disables maskable interrupts by clearing the

PSR.I bit, and executes the interrupt service routine. This

routine can enable nested interrupts by setting the PSR.I

bit, and can use the IENAM Register to control which inter-

rupts are allowed.

INTVECT

PC87570-ICC/VUL 数据表(PDF) 83 Page - National Semiconductor (TI)

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