PC87570-ICCSLASHVUL datasheet(15/168 Pages) NSC

15 / 168 page

Introduction

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The HFCG (High Frequency Clock Generator) provides

clocks for the various on-chip modules. These clocks are

generated directly from a 32.768 KHz crystal or from the on-

chip HFCG. The HFCG generates the high-frequency clock

using the RTC’s 32.768 KHz clock signal as a reference.

The PC87570 operation frequency is set by programming

the HFCG registers. The PMC enables and disables high

frequency clock generation, according to the required pow-

er mode.

The PMC (Power Mode Control) reduces the PC87570's

power consumption to the required activity level. Power

consumption is adjusted by controlling the clock frequency

and selective enabling/disabling of three power modes: Ac-

tive, Idle and Power Off. Activity can be resumed by a peri-

odic wake-up or via external events.

The ICU (Interrupt Control Unit) is a sixteen-channel mod-

ule that interfaces between the interrupt requests (from dif-

ferent on-chip modules and external sources), and the

CR16A core. Both maskable and non-maskable interrupts

are generated.

For maskable interrupts, the ICU controls the masking of

the various sources and prioritizes the different requests. It

generates an interrupt to the core and indicates which of the

sources requested service. For non-maskable interrupts, it

combines the various sources into one and indicates which

is the requested service.

MIWU The Multi-Input Wake-Up module allows the device

to return from Idle mode. The CR16A can enable or disable

the various wake-up conditions. The PC87570 has a total of

23 wake-up signals, some of which are grouped to generate

a single interrupt signal.

GPIO Ports consist of up to 76 GPIO signals that provide

interface and control for the PC system. Some of these I/O

port signals share their pins with an alternate function (see

Table 2-5 on page 27), and may be mutually exclusive.

Some of these signals, when configured as inputs, can in-

terrupt the CR16A when an event is detected even if the de-

vice is in Idle Mode. An example is the SWIN input, which is

dedicated for the PC’s On/Off switch.

One of the I/O pin can be used as an SMI output to the host

processor. The SMI is generated based on various events

identified by the CR16A. This includes an OFF command in-

dication from the APC.

Internal keyboard scanning is supported by 16 open-drain

output port signals, and 8 input port signals with Schmidt

trigger input buffer and internal pull-up resistors. For power

efficiency, the inputs include an interrupt and a wake-up ca-

pability, so that pressing/releasing keys may be identified

without scanning the keyboard matrix in either Active or Idle

modes. The keyboard interrupt is controlled by the MIWU.

The PS/2 Interface, is an industry-standard, with PS/2-

compatible keyboard support, is implemented through a

two-wire, bidirectional TTL interface. Several vendors also

supply PS/2 mouse products and other pointing devices

with the same type of interface.

The PC87570 supports three PS/2 channels. Each channel

has two quasi-bidirectional signals which may be interfaced di-

rectly to an external keyboard, mouse or any other PS/2 com-

patible pointing device. Since the three channels are identical,

the connector ports are interchangeable.

The PC87570 includes a hardware accelerator that allows

the PS/2 channels to be controlled with minimal software

overhead. It also eliminates the sensitivity to interrupt laten-

cy that characterized traditional solutions.

The ACB Interface is a two-wire serial interface compati-

ble with the ACCESS.bus physical layer. It is also compati-

ble with Intel’s SMBus and Philips’ I2C. This module can

serve as a bus master or slave, and performs both transmit

or receive operations.

The MFT16 contains two 16-bit timers with a range of op-

eration modes. These timers can operate from several

clock sources in PWM, Capture or Counter mode to satisfy

a wide range of application requirements.

The TWD has a 16-bit periodic interrupt timer that can be

programmed to generate interrupts at pre-defined intervals.

An 8-bit WATCHDOG timer can reset the PC87570 when-

ever the software loses control of the processor.

The ADC contains eight analog input channels. Each ADC

channel has a 10

µsec minimum conversion period. Either

an internal or external voltage source may be used as a ref-

erence for the A/D conversion.

The DAC has four channels of voltage output. Each of the

four DAC channels has an 8-bit resolution with a full output

range from AGND to AVCC. Conversion time is about 1 µsec

on a 50 pF load.

1.2

EXPANSION OPTIONS

The PC87570 system can be expanded cost effectively, as

follows:

I/O Expansion permits adding I/O port pins, in addition

to those available on-chip, using low-cost standard

74HC devices.

The External Memory may be conﬁgured to 8-bit width

to interface with 8-bit Flash/SRAM devices, or it may

be conﬁgured to 16-bit width when additional perfor-

mance is required.

The PC87570 may be conﬁgured to interface with 32

Kbyte or 56 Kbyte of External Memory (application).

1.3

OPERATING ENVIRONMENTS

Upon power-up reset, the ENV1-0 pins select one the fol-

lowing operating environments:

Internal ROM Enabled (IRE)

Internal ROM Disabled (IRD)

Development (DEV)

See Section 2.4 on page 26 for more information about

these pins and controlling the loads connected to them.

Code written for IRE environment is executable in all environ-

ments, since it is binary compatible. The execution time of

code in on-chip Base Memory (the IRE environment) is identi-

cal to that in off-chip Base Memory (IRD and DEV environ-

ments); i.e., the operation is cycle-by-cycle compatible.

PC87570 devices are tested to ensure that they operate in

either IRE or IRD environment. Only selected parts are test-

ed for operation in DEV environment.

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