ST10F296 datasheet(154/346 Pages) STMICROELECTRONICS

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ST10F296E

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XSSCPORT register

This register is enabled and visible only when the XPEN and XSSCEN bits of the SYSCON

and XPERCON registers respectively are set. However, when SSC1 is disabled, P6, DP6

and ODP6 registers must be used to configure pins P6.2, P6.3, and P6.4.

13.8.2

Alternate functions of Port 6

A programmable number of chip select signals (CS4 to CS0) derived from the bus control

registers (BUSCON4 to BUSCON0) can be output on five pins of Port 6. The other three

pins may be used for bus arbitration to accommodate additional masters in a ST10F296E

system.

The number of chip select signals are selected via Port 0 during reset. The selected value

can be read from bit-field CSSEL in the RP0H register to check the configuration during run

time.

Table 92 summarizes the alternate functions of Port 6 depending on the number of chip

select lines (coded via bit-field CSSEL) that are selected.

XSSCPORT (E880h)

XBus

Reset value: 0000h

-----

---

XODP

6.4

XDP

6.4

XODP

6.3

XDP

6.3

XODP

6.2

-----

---

Table 91.

ODP6 register description

Bit

Bit name

Function

7, 4, 1

XODP6.y

Port open-drain control register XODP6 bit y (y = 2, 3, and 4 only)

0: Port line P6.y output driver in push-pull mode

1: Port line P6.y output driver in open-drain mode

6, 3, 0

XP6.y

Port data register bit XP6 y (y = 2, 3, and 4 only)

5, 2

XDP6.y

Port direction register XDP6 bit y (y = 2, 3, and 4 only)

0: Port line P6.y is an input (high impedance)

1: Port line P6.y is an output

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