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AD9546/PCBZ 数据表(PDF) 25 Page - Analog Devices

部件名 AD9546/PCBZ
功能描述  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9546/PCBZ 数据表(HTML) 25 Page - Analog Devices

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Data Sheet
AD9546
Rev. 0 | Page 25 of 205
HOLDOVER SPECIFICATIONS
Table 20.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
HOLDOVER SPECIFICATIONS
Initial Frequency
Accuracy
±0.01
±0.1
ppb
AD9546 is configured using Device Configuration 1 from Table 37; excludes
frequency drift of SYSCLK source; excludes frequency drift of input
reference prior to entering holdover; 160 ms history timer; history
holdoff setting = 8 decimal in Register 0x1010 and Register 0x1410; three
features (bits) are Logic 1: Bit 4 in Register 0x100E and Register 0x140E,
Bit 3 in Register 0x100E and Register 0x140E, and Bit 5 in Register 0x100E
and Register 0x140E
Relative Frequency
Accuracy Between
Channels
Cascaded DPLL
Operation
0
ppb
Noncascaded DPLL
Operation
<1
ppb
fOSC = 52 MHz (stable external oscillator); fOUT = 155.52 MHz; fREF = 38.88
MHz; DPLL loop bandwidth = 50 Hz; DPLL history accumulation timer = 1
ms; DPLL history holdoff value = 1
History Averaging
Window
0.001
26,8435
sec
ANALOG PLL (APLL0 AND APLL1) SPECIFICATIONS
Table 21.
Parameter
Min
Typ
Max
Unit
VCO FREQUENCY RANGE
Analog PLL0 (APLL0)
2424
3232
MHz
Analog PLL1 (APLL1)
3232
4040
MHz
PFD INPUT FREQUENCY RANGE
162
350
MHz
LOOP BANDWIDTH
260
kHz
PHASE MARGIN
68
Degrees
OUTPUT CHANNEL DIVIDER SPECIFICATIONS
Table 22.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
OUTPUT PHASE ADJUST
STEP SIZE
1
tVCO
VCO time period (tVCO) = 1/(APLLx VCO frequency), where x = 0 or 1
MODULATOR
Carrier Frequency
fVCO/16
Hz
The maximum value is the APLLx VCO frequency divided by 16, where x = 0 or 1;
fVCO is the VCO frequency
Time Deviation (from
Nominal Duty Cycle
of Carrier Clock)
0
216 − 1
tVCO
tVCO = 1/(APLLx VCO frequency), where x = 0 or 1; the maximum value is limited
to the Qxy divide ratio − 1; Qxy refers to the distribution dividers on each
output, where x is either 0 (for PLL0) or 1 (for PLL1), and y is A, B, or C
Embedded Frequency
fOUT/
(228 − 1)
fOUT/6
Hz
fOUT is the output frequency



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