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AD9546/PCBZ 数据表(PDF) 16 Page - Analog Devices |
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AD9546/PCBZ 数据表(HTML) 16 Page - Analog Devices |
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16 / 205 page  AD9546 Data Sheet Rev. 0 | Page 16 of 205 Parameter Min Typ Max Unit VDDIOB = 2.5 V Auxiliary REF0 485 860 1290 ps Auxiliary REF1 365 735 1160 ps Auxiliary REF2 295 690 1135 ps Auxiliary REF3 190 580 1025 ps VDDIOB = 3.3 V Auxiliary REF0 340 620 940 ps Auxiliary REF1 215 500 815 ps Auxiliary REF2 130 455 820 ps Auxiliary REF3 35 340 680 ps M3 VDDIOB = 1.8 V Auxiliary REF0 1095 1585 2135 ps Auxiliary REF1 955 1460 2035 ps Auxiliary REF2 860 1380 1970 ps Auxiliary REF3 790 1310 1905 ps VDDIOB = 2.5 V Auxiliary REF0 550 945 1410 ps Auxiliary REF1 415 820 1300 ps Auxiliary REF2 340 750 1235 ps Auxiliary REF3 275 685 1170 ps VDDIOB = 3.3 V Auxiliary REF0 370 705 1105 ps Auxiliary REF1 285 585 960 ps Auxiliary REF2 210 540 930 ps Auxiliary REF3 145 485 890 ps REFERENCE MONITORS Table 10. Parameter Min Typ Max Unit Test Conditions/Comments REFERENCE MONITORS Reference Monitor tPFD is the nominal phase detector period; tPFD = R/fREF, where R is the frequency division factor determined by the R divider, and fREF is the frequency of the active reference Loss of Reference Detection Time 4.9 + 0.13 × tPFD µs tPFD = R/fREF with fREF in units of MHz Frequency Out of Range Limit 5 × 10−8 0.015 Δf/fREF Minimum deviation from fREF for an unfaulted reference to become faulted; programmable with the lower limit subject to quality of the system clock (or the source of system clock compensation); Δf = frequency deviation from fREF; to prevent false reference invalidation due to the inherent peak jitter of the TDC (TDCJpk), requires fTDC < Threshold × 10−9/TDCJpk, where fTDC is the frequency applied at the TDC input (see the Reference Period Threshold section for the threshold parameter); minimum = 5 × 10−8 requires fTDC < 200 Hz Frequency In Range Limit (5 × 10−8) × (1 – SF) 0.015 × (1 – SF) Δf/fREF Maximum deviation from fREF for a faulted reference to become unfaulted; lower limit subject to quality of the system clock (or the source of system clock compensation); SF = programmable hysteresis scale factor (see Table 54); Δf = frequency deviation from fREF; to prevent false reference revalidation due to TDCJpk requires fTDC < Threshold × 10−9 × SF/TDCJpk, where fTDC is the frequency applied at the TDC input (see the Hysteresis section for SF); minimum = (5 × 10−8) × (1 – SF) requires fTDC < SF × 200 Hz Validation Timer 0.001 1048 sec Programmable in 1 ms steps; maximum is (220 – 1) ms Excessive Jitter Alarm Threshold 1 65,535 ns Programmable in 1 ns steps |
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