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AD9546/PCBZ 数据表(PDF) 32 Page - Analog Devices |
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AD9546/PCBZ 数据表(HTML) 32 Page - Analog Devices |
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32 / 205 page  AD9546 Data Sheet Rev. 0 | Page 32 of 205 SERIAL PORT SPECIFICATIONS SPI Mode Table 35. Parameter Min Typ Max Unit Test Conditions/Comments CSB Valid for VDDIOA = 1.8 V, 2.5 V, and 3.3 V Input Voltage Logic 1 VDDIOA − 0.4 V Logic 0 0.4 V Input Current Logic 1 1 µA Logic 0 1 µA SCLK Input Voltage Logic 1 VDDIOA − 0.4 V Logic 0 0.4 V Input Current Logic 1 1 µA Logic 0 1 µA SDIO As an Input Input Voltage Logic 1 VDDIOA − 0.4 V Logic 0 0.4 V Input Current Logic 1 1 µA Logic 0 1 µA As an Output Output Voltage 1 mA load current Logic 1 VDDIOA − 0.2 V Logic 0 0.2 V SDO Output Voltage 1 mA load current Logic 1 VDDIOA − 0.2 V Logic 0 0.2 V Leakage Current ±1 µA SDO inactive (high impedance) TIMING Valid for VDDIOA = 1.8 V, 2.5 V, and 3.3 V SCLK Clock Rate, 1/tCLK 50 MHz Pulse Width High, tHIGH 5 ns Pulse Width Low, tLOW 9 ns SDIO to SCLK Setup, tDS 2.2 ns SCLK to SDIO Hold, tDH 0 ns SCLK to Valid SDIO and SDO, tDV 9 ns CSB to SCLK Setup, tS 1.5 ns CSB to SCLK Hold, tC 0 ns CSB Minimum Pulse Width High 1 tCLK |
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