AD9546SLASHPCBZ datasheet(20/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 20 of 205

OUTPUT TIMING SKEW BETWEEN Mx PINS AND OUTxyP AND/OR OUTxyN PINS

The timing skew between the Mx pins and the OUTxyP and/or OUTxyN pins is important when using an auxiliary NCO as a reference

input to one of the DPLLs and simultaneously using an Mx pin as an output for the auxiliary NCO (see the Auxiliary NCOs section and

the Status and Control Pins section). To obtain the data given in Table 13, the device configuration uses an auxiliary NCO as the

reference input to DPLL0 and DPLL1, with both phase-locked loop (PLL) channels employing a 1:1 frequency translation from the

auxiliary NCO to the distribution output. The auxiliary NCO output routes to one of the Mx pins that is configured as a status output.

Because of the 1:1 frequency translation, the Mx pin output signal and the OUTxyP/OUTxyN output signal have the same frequency.

The data in Table 13 is for the timing skew between the OUT0AP, OUT0AN, OUT1AP, or OUT1AN pin and the Mx pin carrying the

auxiliary NCO output signal. Note that the auxiliary NCO exhibits ~1.25 ns quantization, and the tabulated data in Table 13 is an average

of the quantization variation.

Table 13.

Parameter

Min

Typ

Max

Unit

TIMING SKEW BETWEEN Mx AND OUT0AP/OUT0AN PINS

VDDIOA and VDDIOB Supply Voltage

1.8 V

−5.5

2.5 V

−5.15

3.3 V

−5.0

TIME DURATION OF DIGITAL FUNCTIONS

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

TIME DURATION OF DIGITAL

FUNCTIONS

EEPROM to Register Download

Time

Using the Typical Configuration conditions from Table 4

Power-On Reset (POR)

Time from power supplies > 80% to release of internal reset

Mx Pin to RESETB Rising Edge

Setup Time

Mx refers to Pin M0 through Pin CSB/M6

Mx Pin to RESETB Rising Edge

Hold Time

Multiple Mx Pin Timing Skew

Applies only to multibit Mx pin functions

RESETB Falling Edge to Mx Pin

High-Z Time

Time from Release of Power-

Down to Completion of

System Clock PLL Calibration

170

µs

Excludes time delay associated with the user programmable

system clock stability timer (50 ms default)

Time from Release of Power-

Down to System Clock PLL

Locked and Calibrated

172

µs

Excludes time delay associated with the user programmable

system clock stability timer (50 ms default)

Time for APLLx to Calibrate and

Lock

Time from assertion of IO update (with Bit 1 = 1 in Register 0x2100

and/or Register 0x2200) to APLLx indicating calibrated and locked

status; uses the Typical Configuration conditions in Table 4;

prerequisites = system clock PLL locked and stable, and DPLLx

phase locked

TIME FROM START OF DPLL

ACTIVATION TO ACTIVE PHASE

DETECTOR OUTPUT

Untagged Operation

tPFD

tPFD = R/fREF, where R is the frequency division factor determined by

the R divider, and fREF is the frequency of the active reference

Tagged Operation

Tag

period

Tag period = (tag ratio/fTAG), where fTAG is either fREF (for tagged

reference mode) or the feedback frequency of DPLLx, fFEEDBACK (for all

other tagged modes); the tag ratio corresponds to the selection of fTAG

(as fREF or fFEEDBACK)

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