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AD9546/PCBZ 数据表(PDF) 21 Page - Analog Devices |
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AD9546/PCBZ 数据表(HTML) 21 Page - Analog Devices |
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21 / 205 page  Data Sheet AD9546 Rev. 0 | Page 21 of 205 DPLL0 AND DPLL1 SPECIFICATIONS Table 15. Parameter Min Typ Max Unit Test Conditions/Comments DPLL Digital Phase Detector (DPD) Input Frequency Range 1 2 × 105 Hz Loop Filter Profile 0 Bandwidth 0.0001 1850 Hz Programmable design parameter; (fPFD/bandwidth) ≥ 20 Phase Margin 70 Degrees Closed-Loop Peaking 1.1 dB Profile 1 Bandwidth 0.0001 305 Hz Programmable design parameter; (fPFD/bandwidth) ≥ 20 Phase Margin 88.5 Degrees Closed-Loop Peaking 0.1 dB In accordance with Telcordia GR-253 jitter transfer specifications DPLL NCO DIVISION RATIO These specifications cover limitations on the freerun tuning word (FTW0) of DPLLx; the AD9546 evaluation software frequency planning wizard sets these values automatically for the user, and the AD9546 evaluation software is available for download from the AD9546 product page at www.analog.com/AD9546; NCO division = 248/FTW0, which takes the form of INT.FRAC, where INT is the integer portion, and FRAC is the fractional portion NCO Integer 7 13 This is the integer portion of NCO division NCO Fraction 0.05 0.95 This is the fractional portion of NCO division DPLL LOCK DETECTION SPECIFICATIONS Table 16. Parameter Min Typ Max Unit Test Conditions/Comments PHASE LOCK DETECTOR Threshold Programming Range 10 224 − 1 ps Threshold Resolution 1 ps FREQUENCY LOCK DETECTOR Threshold Programming Range 10 224 − 1 ps Threshold Resolution 1 ps PHASE STEP DETECTOR Threshold Programming Range 100 232 − 1 ps Setting this value too low causes false triggers Threshold Resolution 1 ps |
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