AD9546SLASHPCBZ datasheet(72/205 Pages) AD

72 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 72 of 205

ANALOG LOOPBACK FEATURE

Figure 55 shows the analog loopback feature of the AD9546

color coded in red. Figure 56 shows a detailed diagram of the

internal structure of the analog loopback feature. The analog

loopback feature uses the REFB and REFBB pins as the analog

loopback input and the M4 pin as the analog loopback output.

The REFB and REFBB inputs both provide loopback paths at

the output of the single-ended receiver (the A path), the input

to the TDC (the B path) and a replica of the reference

demodulator synchronization signal (the C path). Note that the

A path does not provide access to the output of the differential

receiver.

The user selects the desired loopback path via Bits[2:0] of

path based on the operating configuration of the REFB or

REFBB input.

Table 46. Analog Loopback Path Selection

Bits[2:0] (Decimal)

Loopback Path

0 (Default)

Disable loopback

REFB receiver output to M4

REFBB receiver output to M4

REFB divider output to M4

REFBB divider output to M4

REFB demodulator synchronization

output to M4

REFBB demodulator synchronization

output to M4

Reserved

The selection of a loopback path (1 decimal through 6 decimal

in Table 46) substitutes the looped back analog clock signal for

the normal M4 status selection associated with Register 0x0186

(or Register 0x0106; see the Status and Control Pins section for

details). Furthermore, selecting a loopback path does not

automatically complete the loopback path. To complete the

loopback path, the user must enable the M4 output driver by

programming Register 0x0106, Bit 7 = 1.

MEASURING ROUND TRIP DELAY

The analog loopback feature enables the measurement of a

round trip delay. The main goal of a round trip delay

measurement is to quantify the interconnect delay, which tends

to be the dominant time error contributor in a distributed clock

system. A round trip delay measurement assumes the following

three conditions:

•

The DPLL channel operates in zero delay mode

•

The magnitude of the round trip delay is less than the

period of consecutive time stamp events associated with

TS1, TS2, or TS3 (see Figure 55)

•

The frequency of the common clocks is the same as the

frequency of the common clock reference

Operating in zero delay mode is a not a strict requirement, but

greatly simplifies the round trip delay measurement process.

The second and third conditions are not strict requirements,

but if violated, increase the complexity of the round trip delay

computation to a level beyond the scope of this data sheet.

To measure the round trip delay, the user programs one of the

UTS units of the master node to accept time stamps from the

physical clock converter associated with the common clock

reference, TS1 (refer to Figure 55). The UTS converts the TS1

time stamps to TC1 time codes. The user also programs a

second UTS unit to accept time stamps from the physical clock

converter associated with the desired analog loop back path. As

an example, assume the loopback path is from the lower slave

node in Figure 55. In this case, the UTS converts the TS2 time

stamps to TC2 time codes.

AD9546/PCBZ 数据表(PDF) 72 Page - Analog Devices

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