AD9546SLASHPCBZ datasheet(91/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 91 of 205

DISTRIBUTION CLOCK OUTPUT DRIVERS

OVERVIEW

The AD9546 has 10 clock output pins capable of generating up

to 10 output clock signals. The 10 pins comprise two groups of

clocks differentiated by the PLL channel available as the clock

source driving the group. PLL0 can clock the Output 0 group,

and PLL1 can clock the Output 1 group.

The Output 0 group comprises six of the 10 clock output pins

with the six pins consisting of three pin pairs. Each pin pair

represents an output subgroup (A, B, and C) with the pins

designated as

•

OUT0AP and OUT0AN

•

OUT0BP and OUT0BN

•

OUT0CP and OUT0CN

The Output 1 group comprises the remaining four output pins

consisting of two pin pairs. Each pin pair represents an output

subgroup (A and B) with the pins designated as

•

OUT1AP and OUT1AN

•

OUT1BP and OUT1BN

Each output driver has three programmable parameters

controlling

•

Output current direction (source or sink)

•

Output current magnitude

•

Driver configuration

The three control parameters for a given output are bits that

reside in the same register with a register address specific to a

specific output per Table 57.

Table 57. Output Driver Control Register Address

Output

OUT0A

0x10D7

OUT0B

0x10D8

OUT0C

0x10D9

OUT1A

0x14D7

OUT1B

0x14D8

OUTPUT CURRENT CONTROL

Each pin associated with a subgroup pin pair (OUTxyP/OUTxyN,

where x is 0 or 1 and y is A, B, or C) has an output driver and a

channel divider associated with it. Both drivers of an output pin

pair act as either current sources or current sinks. The user

programs the source or sink option via Bit 0 of the appropriate

to current sink mode, and Logic 1 sets both drivers to current

source (or HCSL) mode.

To control the magnitude of the current, use Bits[2:1] of the

appropriate register address in Table 57. Table 58 relates the

value of the two bits to the magnitude of the driver current.

Table 58. Output Driver Current

Bits[2:1] Value (Decimal)

Output Current (mA)

7.5 (default)

12.5

Not applicable

OUTPUT MODE CONTROL

Each output pin pair has two channel dividers and two output

drivers. Figure 66 shows the connectivity between the dividers

and drivers. The divider to driver connectivity depends on the

selected output mode.

FROM

PLL0

PLL1

+1.8V

OUTxyP

Qxy

Qxyy

SINK

SOURCE

DRIVER

OUTxyN

SINGLE-DIVIDER, DIFFERENTIAL DRIVERS

SINGLE-DIVIDER, SINGLE-ENDED DRIVERS

DUAL-DIVIDER, SINGLE-ENDED DRIVERS

FROM

PLL0

PLL1

+1.8V

OUTxyP

Qxy

Qxyy

SINK

SOURCE

DRIVER

OUTxyN

FROM

PLL0

PLL1

+1.8V

OUTxyP

Qxy

Qxyy

SINK

SOURCE

DRIVER

OUTxyN

Figure 66. Output Driver Modes

The user controls the connectivity of the dividers and drivers of

each subgroup pin pair via Bits[4:3] of the appropriate register

address (see Table 57). The value of the two bits selects the

divider to driver relationship per Table 59.

Table 59. Driver Output Mode

Bits[4:3] Value

(Decimal)

Output Driver Mode

Single-divider, differential (default)

Single-divider, single-ended

Dual-divider, single-ended

Not applicable

The single divider modes use only the Qxy divider (with the

Qxyy divider powered down). The dual divider mode makes

use of both the Qxy and Qxyy dividers.

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