AD9546SLASHPCBZ datasheet(93/205 Pages) AD

93 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 93 of 205

OUTPUT DRIVER RESET

Because driver pairs (OUT0AP and OUT0AN, for example) are

configurable as differential or single-ended, when the Q dividers

associated with a driver pair stop toggling (due to a divider

reset, for example), the output state of the driver pair is unknown.

To remedy this uncertainty, the user can force a driver pair to a

known state by means of the various driver reset bits.

Bit 2 of Register 0x2101 allows the user to reset all the driver

pairs of Channel 0. Bit 2 of Register 0x2201 allows the user to

reset all the driver pairs of Channel 1. The user can reset individual

output driver pairs via Bit 5 per the appropriate register

addresses in Table 60.

Table 60. Output Driver Reset Register Address

Output

OUT0AP/OUT0AN

0x2102

OUT0BP/OUT0BN

0x2103

OUT0CP/OUT0CN

0x2104

OUT1AP/OUT1AN

0x2202

OUT1BP/OUT1BN

0x2203

When a driver pair is in a differential configuration, resetting

the driver pair forces the OUTxyP driver to a Logic 0 state and

the OUTxyN driver to a Logic 1 state. When a driver pair is in a

single-ended configuration, resetting the driver pair forces the

OUTxyP and OUTxyN drivers to a Logic 0 state.

OUTPUT MUTING

Manual Output Muting

To mute all the drivers associated with PLL0 or PLL1, use Bit 1

in Register 0x2101 and Register 0x2201 for PLL0 and PLL1,

respectively. To mute individual drivers, use Bits[3:2] per the

appropriate register addresses in Table 60, where Bit 3

corresponds to the OUTxyN driver and Bit 2 corresponds to

the OUTxyP driver.

Automatic Output Unmuting

Automatic unmuting works in conjunction with the

autosynchronization function (see the Autosynchronization

Trigger section). Part of the synchronization sequence involves

synchronously unmuting the output drivers. The AD9546

provides the user options for the timing of the unmuting of the

output drivers.

To select the automatic unmute conditions, use Bits[1:0]

of Register 0x10DC for PLL0 and Register 0x14DC for PLL1.

Table 61 shows the automatic unmute conditions invoked by

these bits. The automatic unmute control applies to PLL0 and

PLL1 independently.

Table 61. Autotmatic Unmute Conditions

Bits[1:0]

(Decimal)

Automatic Unmute Condition

Immediate (default)

Upon activation of a hitless profile

Upon phase lock (hitless mode only)

Upon frequency lock (hitless mode only)

When Bits[1:0] = 0 (decimal), the drivers unmute immediately

upon release of the synchronization request. When Bits[1:0] = 1

(decimal), the drivers do not unmute until release of the

synchronization request and subsequent activation of a hitless/zero

delay profile. When Bits[1:0] = 2 (decimal), the drivers do not

unmute until release of the synchronization request and

subsequent phase lock of the appropriate PLL channel (assu-

ming a hitless/zero delay profile). When Bits[1:0] = 3 (decimal),

the drivers do not unmute until release of the synchronization

request and subsequent frequency lock of the appropriate PLL

channel (assuming a hitless/zero delay profile).

The user can also selectively opt out of the automatic unmuting

feature on a per output basis. For PLL0, use Bits[7:2] of

associated with OUT0CN, OUT0CP, OUT0BN, OUT0BP,

OUT0AN, and OUT0AP, respectively. For PLL1, use Bits[5:2]

of Register 0x14DC where Bits[5:2] correspond to the driver

associated with OUT1BN, OUT1BP, OUT1AN, and OUT1AP,

respectively.

After an automatic mute event occurs for a particular PLL

channel, the user can clear the automatic mute state by setting

Bit 4 of Register 0x2107 for PLL0 and Register 0x2207 for PLL1.

However, this action is generally unnecessary, because the

device automatically clears the automatic mute state whenever

the user changes the state of an automatic unmute bit and issues

an IO update operation.

Output Mute Retiming

If the driver output mutes immediately upon receiving a mute

command, it may result in the output signal shutting off before

the normal falling edge of the associated Q divider output.

Early shutoff of the output signal produces a runt pulse (that is,

the normal Logic 1 period of the Q divider is cut short).

By default, the AD9546 uses a retiming block to prevent the

generation of a runt pulse. However, the user can bypass the

retiming block via Bit 5 per the appropriate register addresses

in Table 57. Bypassing the retiming block causes the output

driver to mute immediately upon receiving a mute command.

AD9546/PCBZ 数据表(PDF) 93 Page - Analog Devices

AD9546/PCBZ 数据表(HTML) 93 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载