AD9546SLASHPCBZ datasheet(65/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 65 of 205

USER TIME STAMPER (UTS)

OVERVIEW

The AD9546 has nine UTSs comprising the UTS system (see

Figure 53). Each UTS in the UTS system converts internal

device time stamps (based on the local time scale) to time codes

based on the common time scale (see the Common Clock

Synchronizer (CCS) section) and makes those time codes

accessible to the user via the register map.

Because the UTS system relies on the common time scale

(which originates with the CCS) the status of the CCS matters

to the UTS system. As such, the UTS system is inoperative

unless the CCS indicates a ready status.

The UTS system consists of nine independent UTSs with each

UTS having a dedicated UTS channel control register. Time

codes output by each UTS route to a readback FIFO. The FIFO

contains time code samples originating from all active

(enabled) UTSs. The FIFO samples include supplemental

information allowing the user to discern the source of a time

code sample and the status of the UTS channel associated with

the time code sample. The FIFO also provides a status related

to its own condition.

The UTS system is independent of the two user time stamp

processors (see the User Time Stamp Processor (UTSP)

section).

UTS CHANNEL CONTROL REGISTERS ADDRESSES

Each UTS channel has a dedicated UTS channel control

UTS Channel x control register occupies a range of register

addresses. UTS 0 occupies Register 0x0E00 to Register 0x0E04.

More generally, UTS x occupies the UTS 0 address range, but

with an offset of x × 0x0005.

UTS CHANNEL ENABLE

Each UTS in the UTS system has an independent enable bit.

The enable bit is Bit 0 in Register 0x0E00 for UTS 0, or more

generally, for UTS x (where x = 0 to 8, integer), add x × 0x0005

to the register address given for UTS 0. Logic 1 enables the

corresponding UTS channel. Logic 0 (default) disables the

corresponding UTS, in which case it stops delivering new time

code samples to the FIFO with no effect on old time code

samples already delivered to the FIFO.

TIME

CODE

SOURCE

FLAGS

OVERFILL

COUNT

READ

BACK

FIFO

IO UPDATE

CCDPLL

UNLOCK

CCR INVALID

CCR FAULT

TIME STAMPS

5 SOURCE

COMMON TIME

SCALE

TIME STAMP

PROCESSOR

ENABLE

TAG

FORMAT

OFFSET

FLAGS

FLAG

ENCODER

TIME

CODE

UTS 0

ENCODED

FLAGS

UTS 1

UTS CHANNEL 1

CONTROL

UTS 8

CCS READY

SOURCE

SELECTOR

NOTES

1. A RANGE OF BITS USES A COLON SEPARATOR

2. ADDRESSES SHOWN FOR UTS CHANNEL CONTROL ARE SPECIFIC TO UTS 0

REG 0x0E01, BITS[4:0]

REG 0x0E01, BIT 5

REG 0x0E00, BIT 1

REG 0x0E00, BIT 0

REG 0x0E00, BITS[4:2]

REG 0x0E04 TO 0x0E02, BITS[23:0]

UTS

CHANNEL 0

CONTROL

REG 0x0E2E, BITS[4:0]

REG 0x0E2E, BITS[7:5]

REG 0x0E2D, BITS[6:0]

REG 0x0E2D, BIT 7

IRQ

REG 0x301C, BITS[7:5]

UTS CHANNEL 8

CONTROL

REG 0x0E3A TO 0x0E2F, BITS[95:0]

Figure 53. UTS System

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