AD9546SLASHPCBZ datasheet(97/205 Pages) AD

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Data Sheet

AD9546

Rev. 0 | Page 97 of 205

DISTRIBUTION PHASE OFFSET CONTROL

OUTPUT PHASE OFFSET OVERVIEW

The phase offset controller (see Figure 67) governs the

application of phase offsets to the individual Q dividers. The

controller implements two categories of phase offset: initial

phase offset and subsequent phase offset.

An initial phase offset applies after the device is powered up or

reset and the user issues a synchronization request that is

completed (see the Distribution Output Clock Synchronization

section). The completed synchronization request results in the

establishment of the initial phase offset. Subsequent phase

offsets apply for all subsequent synchronization requests (that

is, any synchronization requests occurring after the initial

power-up or reset synchronization request). See the

Distribution Output Clock Synchronization section regarding

synchronization requests.

Initial and subsequent phase offsets require the Q divider pulse

width control feature to be turned off (see the Output Pulse

Width Control section).

The initial phase offset depends on a 33-bit unsigned integer in

the register ranges shown in Table 66. The four lower addresses

for each Q divider in Table 66 carry the 32 LSBs of the 33-bit

integer, and Bit 6 of the upper address carries the MSB of the

33-bit integer (Bit 7 is unused and Bits[5:0] apply to other Q

divider features).

Table 66. Q Divider Phase Offset Control Address Ranges

Q Divider

Q0A

0x1104 to 0x1108

Q0AA

0x110D to 0x1111

Q0B

0x1116 to 0x111A

Q0BB

0x111F to 0x1123

Q0C

0x1128 to 0x112C

Q0CC

0x1131 to 0x1135

Q1A

0x1504 to 0x1508

Q1AA

0x150D to 0x1511

Q1B

0x1516 to 0x151A

Q1BB

0x151F to 0x1523

INITIAL PHASE OFFSET

The initial phase offset of a Q divider is dependent on the

divide ratio and state of the half integer divide bit, which

together constitute the number of rising and falling input clock

edges that span one period of the Q divider output. For details

on the divide ratio and half integer divide, see the Distribution

Dividers (Q Dividers) section.

In terms of the values defining the divide ratio of the Q divider,

E = (2 × Divide Ratio) + Half Integer Divide

= 2 × QN

where:

E is the total number of input edges per output period of the Q

divider.

Divide Ratio is the value of the 32-bit integer stored in the

corresponding Q divider register in Table 63.

Half Integer Divide is the value of the corresponding Q divider

half integer divide bit (0 or 1).

QN is the complete divide factor (for example, 101.5) of a

specific Q divider.

Thus, for QN = 101.5, E = 203.

The value of E relates to the phase offset angle, θ, as follows:

θ = 360° × (Phase Offset/E)

where Phase Offset is the integer stored in the phase offset

registers (the phase offset register address ranges appear in

Table 66).

The phase offset angle equation implies that the programmed

phase offset value must be less than E (that is, the phase offset

value has a range of 0 to E − 1). Note that programming an

invalid phase value results in the phase offset controller taking

no action other than setting an error status in Bits[5:0] of

PLL1. For Register 0x310E, Bits[5:0] correspond to Q0CC,

Q0C, Q0BB, Q0B, Q0AA and Q0A, respectively. For Register

0x320E, Bits[3:0] correspond to Q1BB, Q1B, Q1AA, and Q1A,

respectively. The user can access the phase control error results

via an appropriately configured Mx status pin (see the Status

and Control Pins section). The Mx pin output signal constitutes

a logical OR of the six status bits associated with PLL0 or the

logical OR of the four status bits associated with PLL1.

SUBSEQUENT PHASE OFFSETS

Subsequent phase offsets involve writing a new 33-bit phase

offset value to the appropriate Q divider per Table 66 and then

setting the IO update bit. The magnitude of the applied phase

offset is the same as described in the Initial Phase Offset

section.

Unlike the initial phase offset, the phase controller implements

subsequent phase offsets in stepwise fashion as a sequence of

phase steps, where the 33-bit phase offset value denotes the

amount of phase offset present at the termination of the sequence.

The controller executes the phase steps at a rate commensurate

with the Q divider output period. This mechanism makes it

possible to soften the phase transient that results when applying

subsequent phase offsets. The reason is the stepwise

implementation of the phase offset effectively limits phase

transients to some maximum amount per output cycle of the

Q divider, which effectively constitutes a phase rate of change

limiter. The limited rate of change of the phase replaces the

relatively large instantaneous phase step of a phase adjustment

with a series of small phase steps, thereby reducing the spectral

content normally associated with phase adjustment.

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