AD9546SLASHPCBZ datasheet(85/205 Pages) AD

85 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 85 of 205

However, because the user knows the source is no longer

traceable, the user can force the reference to be invalid by

making invalidate = 1 (even though the reference monitor sees

the reference as being in tolerance). The user can reinstate a

valid status when conditions permit by making invalidate = 0.

However, if the reference signal goes out of tolerance (as

determined by the reference monitor) during the time that

invalidate = 1, then when the user makes invalidate = 0, the

reference remains invalid. That is, the user cannot force a

reference with an invalid status to a valid status via the fault

reference bit when bypass = 0.

A scenario for using bypass = 1 (that is bypassing reference

monitor control of the validation timer) is when a reference

signal is of the gapped clock variety. A reference signal

employing a gapped clock is problematic for the reference monitor

because it cannot reliably discern an in or out of tolerance

condition. As such, an otherwise unfaulted reference can be

deemed faulted from the point of view of the reference

monitor. Under such conditions, the user can bypass reference

monitor control of the validation timer (and thereby valid and

invalid status) by making bypass = 1. With bypass = 1, the

invalidate control bit allows the user to mimic the fault and

unfault conditions normally generated by the reference

monitor.

DISCONTINUITY DETECTION

The reference monitor detects the following discontinuities in

the period of the reference signal:

•

An absent reference signal or a reference period that

deviates by more than 3.125% of the expected value.

•

A reference period sample deviating by more than 64 times

JEST plus ½ of jitter tolerance, where JEST is the current

estimate of the jitter variance.

•

Short term jitter exceeds long-term jitter by ~50%.

Detection of a discontinuity causes the discontinuity status

signal (see Figure 60) to be Logic 1.

REFERENCE PERIOD JITTER ESTIMATION

Because the reference monitor uses numeric time stamps to

measure the reference period, it can estimate the mean and

variance of the reference signal as it observes period samples

(that is, the difference between successive time stamps from the

TDC). The mean is an estimate of the reference period, and the

variance is an estimate of the jitter present on the reference

signal. The reference monitor uses the mean and jitter variance

estimate to make in tolerance or out of tolerance decisions by

comparing a span of 16 times the current jitter variance

estimate (±8σ) against the tREF, threshold, and hysteresis

parameters. This statistical approach allows the reference

monitor to make tolerance decisions with a high degree of

confidence in a nearly optimal minimum observation time.

REFERENCE MONITOR DECISION TIME

The reference period estimation algorithm takes into account

the value of the threshold parameter specified by the user (see

the Reference Monitor Controls section) and the actual jitter

present on the reference signal. In general, less averaging

required by the jitter estimator to bring the variance within a

suitable range means a shorter decision making time. The key

point is that both the value of the threshold parameter and the

amount of jitter present on the input signal govern the decision

time for the reference monitor to declare an out of tolerance

condition. That is, the decision time is not deterministic.

Although jitter plays a role in the decision time of the reference

monitor under normal operation, jitter has little effect on the

decision time when the reference period is much greater than

the base period or when the reference signal disappears

completely. The reason is the reference monitor has advance

knowledge of the expected period of the reference signal

(namely, R × tREF). Thus, the reference monitor can rely on

internal timing (rather than TDC time stamps) to keep watch

for expected time stamps from the TDC. If the reference

monitor fails to observe the arrival of a new time stamp after a

period of 1.15 × R × tREF, the monitor declares an LOS.

Note that for an input signal that is slow (but not absent), after

the first assertion of LOS status, the LOS status toggles on each

subsequent occurrence of the expected period of the reference.

Thus, the LOS bit is not a reliable indicator of the loss of the

reference signal. Instead, use the fault status as an indicator of

the loss of the signal.

REFERENCE VALIDATION

Some applications require a reference to be in an unfaulted

condition for a prescribed period before exhibiting valid status.

To accommodate these applications, the reference monitor

includes a programmable validation timer. A reference

transition from a faulted state to a nonfaulted state indicates a

start event for the validation timer, which begins counting

down. Upon expiration of the timer, valid = 1, which indicates

the reference is available for use (see Figure 60).

It is important to note that the validation timer stops counting

down and resets upon the occurrence of the faulted status (fault

= 1). A subsequent unfault condition causes the timer to

reinitiate a countdown from the programmed tVALID value.

Thus, the reference only attains valid status when the reference

remains unfaulted for the full duration of the validation timer.

The user has the option to force the validation timer to jump to

the end of its timing function by programming timeout = 1 (see

the Reference Monitor Controls section and Figure 60). In this

way, if a faulted reference has returned to a nonfaulted state

and is awaiting validation, the user can override the timer if

necessary, and immediately bring the reference to a valid status.

Programming timeout = 1 has no effect on a faulted reference

because a fault condition resets the validation timer.

AD9546/PCBZ 数据表(PDF) 85 Page - Analog Devices

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