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AD9546/PCBZ 数据表(PDF) 77 Page - Analog Devices

部件名 AD9546/PCBZ
功能描述  Dual DPLL Digitized Clock Synchronizer
PDF  205 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9546/PCBZ 数据表(HTML) 77 Page - Analog Devices

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Data Sheet
AD9546
Rev. 0 | Page 77 of 205
REFERENCE CLOCK INPUT RESOURCES
The AD9546 has eight reference clock inputs as shown in
Figure 59. The eight inputs comprise two groups of four:
Four primary reference inputs (REFA, REFAA, REFB, and
REFBB)
Four auxiliary reference inputs (auxiliary REF0, auxiliary
REF1, auxiliary REF2, and auxiliary REF3)
The two groups are functionally identical except for the
configuration of their input receivers.
The primary reference inputs have configurable input receivers
(see the Reference Receivers section) and dedicated pins. The
user can configure the REFA and REFAA inputs as a single
differential receiver or as two independent, single-ended
receivers. The REFB and REFBB inputs can be configured
likewise.
The auxiliary reference clock inputs have nonconfigurable,
single-ended CMOS receivers, and rather than having
dedicated pins, they are accessible only through Mx Pins (see
the Status and Control Pins section).
Each reference clock input has a dedicated reference monitor,
reference divider (R divider), TDC, and reference demodulator.
AD9546
TIME STAMPS
REFA
REFAA
REFB
REFBB
TIME STAMPS
TIME STAMPS
TIME STAMPS
TIME STAMPS
TIME STAMPS
TIME STAMPS
TIME STAMPS
AUX REF0
AUX REF1
AUX REF2
AUX REF3
M0
M1
M2
M3
M4
SDO/M5
CSB/M6
DEMOD
TDC
REF
MON
÷R
DEMOD
REF
MON
DEMOD
TDC
REF
MON
÷R
DEMOD
REF
MON
DEMOD
TDC
REF
MON
÷R
Mx PIN
FUNCTION
LOGIC
Figure 59. Reference Inputs Block Diagram



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