AD9546SLASHPCBZ datasheet(68/205 Pages) AD

68 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 68 of 205

FIFO Count

The FIFO provides sample count information via the 7-bit

FIFO status count bit field in Bits[6:0] of Register 0x0E2D.

During normal operation (that is, overfill = 0), the FIFO status

count bit field value indicates the number of time code samples

currently in the FIFO. The user has access to the not empty

status of the FIFO (that is, when the value of Bits[6:0] of

configured Mx status pin. However, when FIFO overfill = 1, the

FIFO status count bit field value indicates the number of lost

time code samples. That is, the meaning of the value in the

FIFO status count bit field changes based on the status of the

FIFO overfill bit.

A transition of the FIFO status count bit field from a value of

zero to a nonzero value is an indication that the FIFO is not

empty. That is, the FIFO was empty (FIFO status count = 0) but

now the FIFO has one (or more) time code samples (FIFO

status count ≠ 0) available for reading by the user. The zero to

nonzero transition appears as a status flag as part of the IRQ

mechanism (see the Interrupt Request (IRQ) section) via Bit 5

of Register 0x301C. The not empty status of the FIFO is also

available via an appropriately configured Mx status pin (see the

Status and Control Pins section).

The Mx pin status indication of FIFO not empty remains

asserted until the FIFO becomes empty (FIFO status count = 0).

Reading Back FIFO Data

The FIFO captures time code samples (up to 18) and status

information associated with those time code samples from all

the enabled UTS channels. Because each FIFO sample consists

of a time code and status information, reading time code

samples from the FIFO requires a sequence of operations.

When the FIFO receives a new UTS sample, it flags an IRQ via

Bit 6 of Register 0x301C.

First, the user asserts an IO update (Bit 0 in Register 0x000F),

which latches the FIFO overfill and FIFO count status bits into

the register map. If the user reads the previous time code from

the register map prior to asserting an IO update, the FIFO shifts

the contents and the next available FIFO sample overwrites the

previous contents in the register map upon an IO update

assertion. The FIFO does not shift the contents unless the user

had previously read the time code from the register map prior

to the assertion of an IO update. Thus, the user is free to read

the current FIFO time code multiple times as long as the user

does not assert an IO update.

Next, the user reads the FIFO status. If the FIFO count is zero,

the FIFO is empty and there is no need to continue. If the FIFO

count is nonzero and the FIFO overfill bit is Logic 0, the time

code value in the register map is ready for reading. However, if

the FIFO overfill bit is Logic 1, the FIFO is in an overflow

condition and time code samples have been lost. In an overflow

condition, the FIFO count value indicates how many samples

were lost. The FIFO count value has a limit of 127. Therefore,

there is no way to determine if more than 127 samples were

lost. Upon reaching an overflow condition, the FIFO does not

accept new time code samples. However, the contents remaining

in the FIFO are valid but may be too old to be useful.

Finally, assuming the FIFO status is not empty and not in an

overflow condition, the user may read the time code as well as

the source code and encoded status bits associated with the

current FIFO sample. The user can read the existing time code

and status information repeatedly, provided the IO update

remains unasserted. Assertion of an IO update overwrites the

the register map prior to asserting an IO update.

AD9546/PCBZ 数据表(PDF) 68 Page - Analog Devices

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