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AD9546/PCBZ 数据表(PDF) 69 Page - Analog Devices |
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AD9546/PCBZ 数据表(HTML) 69 Page - Analog Devices |
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69 / 205 page  Data Sheet AD9546 Rev. 0 | Page 69 of 205 INVERSE USER TIME STAMPER (IUTS) OVERVIEW The AD9546 has two IUTSs: IUTS 0 and IUTS 1 (see Figure 54). As the name implies, an IUTS performs the inverse function of a UTS: accepting time codes based on the common time scale provided by the user via the register map and converting those time codes to internal device time stamps based on the local time scale (see the Common Clock Synchronizer (CCS) section). Because the IUTSs rely on the common time scale (which originates with the CCS), the status of the CCS matters for the proper function of an IUTS. As such, each IUTS is inoperative unless the CCS indicates ready status. The intended operation of an IUTS is to translate a digitized clock signal (provided by the user in the form of a periodic sequence of time codes written to the register map) to an internal digitized clock signal for use by other resources within the AD9546 (for example, as the input to one of the DPLL channels). In a real-world, typical digitized clocking application, the user reads time codes from a UTS and delivers those time codes to an IUTS, which constitutes the transport of a digitized clock signal (see Figure 49). In operation, the user writes a time code to an IUTS and asserts an IO update. The writing of a time code and subsequent assertion of an IO update causes the IUTS to process the new time code. Repeatedly carrying out the process of writing a time code and asserting an IO update effectively constitutes a digitized clock signal. The IUTS computes the period of successive time codes via the period processor, where the current time code minus the previous time code constitutes an instantaneous period sample. Because period samples may exhibit jitter from sample to sample, the period processor employs an averaging mechanism to filter out period jitter from the underlying digitized clock signal. The averaging mechanism allows the period processor to provide a reliable estimate of the next time code in the sequence, despite the presence of period jitter on the incoming sequence of time codes. The IUTS does not produce an output time stamp from the estimated time code until the time indicated by the common time scale is greater than or equal to the value of the estimated time code. That is, a causal gateway prevents estimated time codes from appearing as output time stamps until they are current (in terms of the common time scale). The period processor of the IUTS includes a period monitor that observes the period of each time code sample processed. If a period sample deviates by more than about 1.5625%, the IUTS that processed the sample indicates an invalid status (see the IUTS Status section). ESTIMATED TIME CODE STATUS BYPASS LOCK PERIOD PROCESSOR PERIOD MONITOR REG 0x0F00, BIT 1 IUTS 0 COMMON TIME SCALE CAUSAL GATEWAY TIME STAMP COMMON TIME SCALE TIME STAMPS CCDPLL UNLOCK CAUSAL GATEWAY OFFSET BYPASS LOCK 24 TIME STAMP CCS READY ADJUSTED TIME CODE PERIOD PROCESSOR PERIOD MONITOR REG 0x0F00, BIT 0 REG 0x0F03 TO 0x0F01, BITS[23:0] REG 0x0F04, BIT 0 REG 0x0F04, BIT 1 REG 0x0F07 TO 0x0F05, BITS[23:0] CSS SYNC 0 TIME CODE TO COMMON CLOCK SYNCHRONIZER 96 REG 0x0F15 TO 0x0F0A, BITS[95:0] CSS SYNC 1 TIME CODE IUTS 0 TIME CODE IUTS 1 TIME CODE FORMATTER REG 0x0F09, BIT 7 FORMAT 96 96 96 96 FORMATTED TIME CODE IUTS 0 RESTART CSS SYNC 1 RESTART CSS SYNC 0 RESTART RESTART REG 0x0F08, BIT 0 DESTINATION 5 REG 0x0F09, BITS[4:0] TIME CODE OFFSET 24 96 IUTS 1 RESTART IUTS 1 INVALIDATE REG 0x3023, BIT 0 REG 0x301E, BITS[1:0] ESTIMATED TIME CODE ADJUSTED TIME CODE STATUS REG 0x3023, BIT 1 REG 0x301E, BITS[3:2] COMMON TIME SCALE NOTES 1. A RANGE OF BITS USES A COLON SEPARATOR Figure 54. IUTS Block Diagram |
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