AD9546SLASHPCBZ datasheet(76/205 Pages) AD

76 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 76 of 205

of calibrating, status Bit 2 of Register 0x3001 indicates busy

(Logic 1).

Bit 1 of Register 0x2000 provides an alternate means to

calibrate the system clock PLL (this bit also calibrates APLL0

and APLL1).

Although the AD9546 has a variety of power-down modes,

including a specific system clock power-down, it is not

necessary to calibrate the system clock when recovering from

any of the power-down modes. However, recovering from a

power-down of the system clock necessitates calibration of the

APLLs due to the loss of the system clock during its power-down.

SYSTEM CLOCK STABILITY COMPENSATION

An application requiring low DPLL loop bandwidth

necessitates the use of a very stable system clock source. Using a

relatively unstable system clock source like a crystal resonator

or crystal oscillator, for example, in conjunction with the DPLL

having a very narrow loop bandwidth (less than approximately

50 Hz) may cause the DPLL to unlock or experience

intermittent unlock events. The typical solution requires the

use of a very stable system clock source (an OCXO, for

example). An alternate solution uses the integrated system

clock compensation of the AD9546, which enables the use of a

crystal resonator as the system clock source. The basic concept

is the connection of a crystal resonator (25 MHz to 80 MHz) to

the XOA and XOB pins per Figure 30, which capitalizes on the

exceptional phase noise performance of the crystal.

However, the crystal resonator lacks the desired stability. Instead,

the stability arises via the connection of a highly stable source

(for example, TCXO, OCXO, or GPS) to an unused REFx or

Mx input. The stable source then serves as the reference

frequency to the system clock compensation feature of the

device (see the System Clock Compensation section). The

system clock compensation feature allows the device to benefit

from both the stability of the highly stable source and the

exceptional phase noise performance of the crystal resonator.

Thus, the system clock compensation feature provides a

mechanism to employ a low loop bandwidth DPLL (as required

by the application) even though the system clock source is a

relatively unstable crystal resonator.

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