AD9546SLASHPCBZ datasheet(48/205 Pages) AD

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AD9546

Data Sheet

Rev. 0 | Page 48 of 205

THEORY OF OPERATION

Figure 1 summarizes the fundamental building blocks of the

AD9546. The core of the device comprises two independent

PLLs, PLL0 and PLL1, as well as proprietary resources enabling

the digital transport of clock signals (digitized clocking)

between multiple AD9546 devices over a single digital link.

Digitized clocking streamlines the design of systems that rely

on the transport of time scales between spatially separated

devices. The digitized clocking functionality comprises a common

clock DPLL (CCDPLL), a common clock Synchronizer (CCS),

nine user time stampers (UTS 0 to UTS 8), and two inverse user

time stampers (IUTS 0 and IUTS 1).

The AD9546 provides a high degree of backward compatibility

(legacy) with the AD9545, but with enhancements to support

digitized clocking. The user activates most enhancements

individually via register programming. Activating certain

enhancements may affect legacy functionality and override

settings in the registers associated with legacy functionality. In

such cases, text describing a specific enhancement in this data

sheet expressly states any impact on legacy functionality or

The AD9546 synthesizes its system clock via a system clock PLL

that upconverts the frequency applied to the system clock input

pins, XOA and XOB. The system clock input pins accept

frequencies from 20 MHz to 300 MHz from an external clock

source. Alternatively, the user can connect a crystal resonator

(25 MHz to 80 MHz) directly across the XOA and XOB pins.

The output of the system clock PLL is the primary time base for

time keeping functions within the AD9546.

The AD9546 supports up to eight reference input clock signals (via

the REFA, REFAA, REFB, and REFBB pins and four appropriately

configured Mx pins feeding auxiliary REF0, auxiliary REF1,

auxiliary REF2, and auxiliary REF3). Each reference input has a

dedicated reference divider as well as a reference monitor to detect

when the reference signal is lost or compromised. Furthermore,

when the AD9546 detects a faulty reference, it can automatically

switch to another (valid) reference with the user-programmable

reference selection priority.

The user also has access to two independent auxiliary NCOs.

These NCOs provide for internally generated frequencies up to

65,535 Hz with a tuning resolution of 2−40 Hz (approximately

1 pHz).

The DPLL portion of each PLL channel includes a programmable

digital loop filter with extremely low loop bandwidth capability.

Low loop bandwidth capability enables a significant reduction

of jitter transfer from the reference input to the output. Each

DPLL provides precise frequency translation by means of a 48-bit

NCO capable of generating clock signals in the range of 162 MHz

to 350 MHz. Furthermore, both DPLLs enable support of

manual or automatic transition to holdover operation.

Holdover operation constitutes the device generating an output

frequency synthesized from the system clock (as opposed to

translating a frequency from a reference input to an output).

During holdover operation, the AD9546 continuously provides

an output clock signal while the system clock is present. The

AD9546 is also capable of setting the holdover output

frequency based on a time average of the output frequency

history prior to the transition to holdover operation.

The output signal from the DPLL routes to the input of the APLL,

which upconverts the signal to a range of 2.424 GHz to 3.232 GHz

(APLL0) or 3.232 GHz to 4.040 GHz (APLL1). A high frequency

divider (÷2) follows the APLL VCO output providing a factor of 2

frequency reduction prior to delivery to the clock distribution

section.

The clock distribution section consists of a bank of dividers (Q)

and output drivers dedicated to each output pin. The PLL0 channel

has six Q divider/driver units, whereas the PLL1 channel has

four Q divider/driver units. Each Q divider has 32-bit program-

mable division depth and programmable phase offset control.

The drivers operate up to 500 MHz and are configurable as a

single-ended or differential output with adjustable output

current (7.5 mA, 12.5 mA, or 15 mA).

The AD9546 includes an integrated temperature sensor and

system clock compensation circuitry, which allows the device to

adjust automatically for frequency drift errors associated with

the system clock source.

AD9546/PCBZ 数据表(PDF) 48 Page - Analog Devices

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