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AD9546

Data Sheet

Rev. 0 | Page 52 of 205

DIGITIZED CLOCKING

OVERVIEW

Digitized clocking enables precise timing transport (frequency

and phase) among spatially separated devices by the exchange

of numeric time codes to synchronize local clocks (assuming all

devices have access to a common reference clock signal).

A digitized clocking system comprises multiple timing nodes

with each node relying on a shared external time base

(common clock reference). Because each node shares the same

common clock reference, each node increments at the same

rate, resulting in all nodes having the same time scale. Although

all the nodes have the same time scale, there is no guarantee

they share the same epoch. Digitized clocking relies on a user

provided synchronization signal at each node to establish a

common epoch, ultimately leading to all nodes being time

aligned. A unique characteristic of digitized clocking is the

ability to exchange numeric time codes between nodes via a

digital bus, which provides a means to send multiple clocks

over one digital bus (clock aggregation) instead of having to

route multiple analog clock signals throughout a system. The

AD9546 contains all the necessary building blocks to

implement one digitized clocking node.

Figure 48 shows the individual components of a complete

digitized clock node as implemented in the AD9546. These

digitized clocking components include the following:

•

A system clock PLL for generating a system clock

frequency for internal digital timing functions (see the

System Clock PLL section)

•

A common clock DPLL to phase lock to a reference time

base (common clock reference) and maintain a local time

scale

•

A physical clock converter for converting the rising edges

of a physical clock to time stamps derived from the system

clock

•

A physical clock generator for converting time stamps

derived from the common time scale to a physical clock

output signal

•

A CCS for creating a common time scale by assigning an

epoch to the local time scale

•

A UTS to convert internal time stamps to time codes based

on the common time scale and provide those time codes to

the user for external use

•

An IUTS to convert a series of time codes based on the

common time scale (a digitized clock signal) provided by

the user to internal time stamps

Figure 48 shows a variety of time stamp sources. Certain

digitized clocking components require the ability to connect to

any one of the time stamp sources, which is the reason those

components include a time stamp selection mux at their input.

SYSTEM CLOCK PLL COMPONENT

The system clock PLL typically uses an external crystal

resonator as a frequency source, which tends to offer optimal

overall phase noise performance. The system clock PLL

synthesizes a high frequency internal system clock signal

(~2.4 GHz) from the external frequency source, which provides

the basic internal timing for the device. The TDCs of the device

use the system clock to generate time stamps (see the Time to

Digital Converter (TDC) section).

Note that the internal system clock signal is one of the two

frequency sources the common clock DPLL component uses to

generate the local time scale.

COMMON CLOCK DPLL COMPONENT

The purpose of the common clock DPLL is to produce a local

time scale. The common clock DPLL uses the system clock for

internal timing, but the phase locks to a reference time base, the

common clock reference. The output of the common clock

DPLL is the local time scale, which constitutes the accumulated

period of cycles of the common clock reference and provides an

internal sense of time for the digitized clocking components.

The inherent closed-loop architecture of the common clock

DPLL results in the generation of an error signal, Correction

Factor 3 (CF3), that effectively compensates for system clock

fluctuations. Note the CF3 signal is available to the system clock

compensation functional block of the AD9546 (see the

Compensation Method 3 section).

PHYSICAL CLOCK CONVERTER

The physical clock converters provide an input to receive an

external clock signal, provide optional integer frequency

division, and convert rising clock edges to numeric time

stamps. The time stamps are then available for use by those

digitized clocking components that require a time stamp

source.

PHYSICAL CLOCK GENERATOR

The physical clock generator makes use of the AD9546 DPLL

channels and output distribution drivers to produce an analog

clock output signal from time stamps. In a digitized clocking

application, the time stamps derive from the common time

scale. Because the DPLL can accept those time stamps as its

reference input, the output of the physical clock generator

consists of analog clock signals.

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