AD9546SLASHPCBZ datasheet(98/205 Pages) AD

98 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 98 of 205

When the Q divider is in the process of phase slewing as a part

of the phase offset sequence, the phase offset controller indicates

phase slew active status via Bits[5:0] of Register 0x310D and

Bits[3:0] of Register 0x320D. For Register 0x310D, Bits[5:0]

correspond to Q0CC, Q0C, Q0BB, Q0B, Q0AA, and Q0A,

respectively. For Register 0x320D, Bits[3:0] correspond to

Q1BB, Q1B, Q1AA, and Q1A, respectively.

The user can access the phase slew active results via an

appropriately configured Mx status pin (see the Status and

Control Pins section). The Mx pin output signal constitutes a

logical OR of the six status bits associated with PLL0 or the

logical OR of the four status bits associated with PLL1.

Maximum Phase Slew Step Size

During the execution of a subsequent phase offset, the user

controls the maximum step size of the phase steps for a

particular Q divider via Bits[2:0] per the same address given in

Table 64. The value stored in Bits[2:0] establishes the maximum

phase step size per Table 67 (in which E is the number of Q

divider input edges per output period (see the Initial Phase

Offset section) and floor(x) means to round x to the nearest

integer in the direction of −∞). Keep in mind that Table 67

defines a maximum phase step size during phase slewing, but

the controller may use smaller values to ensure the terminal

phase value does not exceed the programmed phase offset

value.

When Bits[2:0] = 7 decimal, the phase controller requires only

one step to reach the desired phase offset regardless of the size of

the phase offset. Therefore, the bit setting effectively deactivates

the phase slewing feature. When Bits[2:0] = 7, the phase

controller behaves as though the phase slew mode bit is Logic 0

(that is, lag only) even if the phase slew mode bit is Logic 1 (see

the Phase Slew Mode section).

When Bits[2:0] = 0 or 1 decimal, the slewing operation is

limited to half-cycles or full cycles, respectively, of the input

clock. Because a 0 or 1 setting represents the smallest possible

maximum phase step for most Q divider divide ratios, most

choices of phase offset result in phase slewing as though the

maximum phase slew step was set to 0 or 1.

Maximum phase slew step values greater than 1 decimal require

the user to ensure that the maximum phase step size is greater

than or equal to one input half-cycle. Otherwise, the phase slewing

function is invalid, in which case the device flags an error via the

control error bits described in the Initial Phase Offset section.

For example, when QN = 5 (that is, E = 10 (see the Initial Phase

Offset section)), one half-cycle constitutes 36°. As such,

maximum phase slew step values of 2 or 3 are invalid, and the

controller sets the appropriate error flag.

Table 67. Maximum Phase Slew Step Size

Bits[2:0]

(Decimal)

Maximum Phase

Step Size (Degrees)

Comment

360 ÷ E

One input half-cycle

180 ÷ E

Two input half-cycles

360 × floor(E/32)/E

~11.25°

360 × floor(E/16)/E

~22.5°

360 × floor(E/8)/E

~45°

360 × floor(E/4)/E

~90°

360 × floor(E/2)/E

~180°

7 (Default)

360 × (E − 1)/E

~360°

Phase Slew Mode

During the execution of a subsequent phase offset, the phase

controller can slew phase in two different modes. The user selects

the mode via Bit 3 per the same address given in Table 64.

When Bit 3 = 0 (default), the phase controller slews phase in the

direction that reduces the output frequency during the stepwise

phase adjustment sequence. Alternatively, when Bit 3 = 1, the

phase controller slews phase in the direction requiring the

fewest number of steps. However, when the half integer divide

bit is Logic 1 and the desired phase shift is within one Q divider

input half-cycle of the midpoint of an output cycle, the phase

controller may choose the slightly longer direction.

When Bit 3 = 1, the output frequency may change in either

direction, as required, for any given stepwise phase adjustment

sequence (due to the phase controller choosing the direction of

the fewest number of steps).

Output Pulse Width Control

By default, the Q divider output generates a clock signal with a

50% pulse width. However, the user has the option to control

the pulse width of the Q divider output. The control granularity

is one half cycle of the input clock of the Q divider. Pulse width

control is via Bit 4 per the same address given in Table 64.

When Bit 4 = 0, the phase offset controller uses the

programmed 33-bit phase offset as a phase offset (as described

in the Initial Phase Offset section). When Bit 4 = 1, the 33-bit

phase offset value defines a pulse width rather than a phase

offset.

The pulse width, in percent, is given by

Pulse Width (%) = 100 × Phase Offset/E

(2)

where:

Pulse Width defines the portion of an output clock cycle from

the rising edge to the falling edge.

Phase Offset is the integer stored in the phase offset registers.

Table 66 shows the phase offset register address ranges.

E is as defined in the Initial Phase Offset section.

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