AD9546SLASHPCBZ datasheet(45/205 Pages) AD

45 / 205 page

Data Sheet

AD9546

Rev. 0 | Page 45 of 205

200

400

600

800

1000

1200

1400

1600

1800

2000

100

10k

100k

10M

100M

FREQUENCY (Hz)

CML, DIFFERENTIAL, 15mA

CML, DIFFERENTIAL, 12.5mA

CML, DIFFERENTIAL, 7.5mA

HCSL, DIFFERENTIAL, 15mA

HCSL, DIFFERENTIAL, 12.5mA

HCSL, DIFFERENTIAL, 7.5mA

Figure 21. Differential Peak-to-Peak Voltage Swing vs. Frequency;

HCSL Drivers Terminated 50 Ω to Ground per Figure 39;

CML Drivers Terminated 50 Ω to 1.8 V per Figure 40

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

TIME (ns)

–50

–40

–30

–20

–10

CLOAD = 5pF

CLOAD = 10pF

CLOAD = 20pF

Figure 22. Mx Pin Waveforms for Various Load Conditions; Normal Output

Drive Strength (Default); VDDIOx = 1.8 V

–30

–25

–20

–15

–10

–5

0.001

0.01

0.1

OFFSET FREQUENCY (Hz)

100

1000

BW = 0.01Hz

BW = 0.1Hz

BW = 1Hz

BW = 10Hz

BW = 100Hz

PHASE MARGIN:70°

PEAKING: 1.07dB

ATTENUATION:

AT LOOP BW: 2.5dB

2× LOOP BW: 21dB/

DECADE

100× LOOP BW: 60dB/

DECADE

Figure 23. DPLL Closed-Loop Transfer Function Nominal Phase Margin

Loop Filter Setting

–30

–25

–20

–15

–10

–5

0.001

0.01

0.1

100

OFFSET FREQUENCY (Hz)

BW = 0.01Hz

BW = 0.1Hz

BW = 1Hz

BW = 10Hz

BW = 100Hz

PHASE MARGIN: 88.5°

PEAKING: <0.1dB

ATTENUATION:

AT LOOP BW: 5.5dB

2× LOOP BW: 18dB/DECADE

100× LOOP BW: 41dB/DECADE

1000× LOOP BW: 60dB/DECADE

Figure 24. DPLL Closed-Loop Transfer Function High Phase Margin Loop

Filter Setting

150

–75

–25

100

125

–50

–50 –40 –30 –20 –10 0

10 20 30 40 50 60 70 80

100

110

AD9546 DIE TEMPERATURE (°C)

DIFFERENTIAL CML OUTPUTS- UNCOMPENSATED

SINGLE- ENDED CML OUTPUTS- UNCOMPENSATED

DIFFERENTIAL CML OUTPUTS- COMPENSATED

SINGLE- ENDED CML OUTPUTS- COMPENSATED

Figure 25. Propagation Delay Variation vs. AD9546 Die Temperature; CML

Output Mode; 1.2 V CMOS Reference Input Mode; fSYS = 2392 MHz; Internal

Zero Delay (Hitless) Mode

150

–75

–25

100

125

–50

–40 –30 –20 –10 0

10 20 30 40 50 60 70 80

100

110

AD9546 DIE TEMPERATURE (°C)

DIFFERENTIAL CML OUTPUTS- UNCOMPENSATED

SINGLE- ENDED CML OUTPUTS- UNCOMPENSATED

DIFFERENTIAL CML OUTPUTS- COMPENSATED

SINGLE- ENDED CML OUTPUTS- COMPENSATED

Figure 26. Propagation Delay Variation vs. AD9546 Die Temperature; HCSL

Output Mode; 1.2 V CMOS Reference Input Mode; fSYS = 2392 MHz; Internal

Zero Delay (Hitless) Mode

AD9546/PCBZ 数据表(PDF) 45 Page - Analog Devices

AD9546/PCBZ 数据表(HTML) 45 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载