AD9546SLASHPCBZ datasheet(4/205 Pages) AD

4 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 4 of 205

Half Integer Division ................................................................. 96

Q Divider Reset........................................................................... 96

Q Divider Constraints ............................................................... 96

Hitless/Zero Delay Feedback.................................................... 96

Distribution Phase Offset Control............................................... 97

Output Phase Offset Overview................................................. 97

Initial Phase Offset ..................................................................... 97

Subsequent Phase Offsets.......................................................... 97

Distribution N Shot/PRBS Output Clocking ........................... 100

N Shot/PRBS Clocking Overview .......................................... 100

Randomized Clock (PRBS)..................................................... 101

N Shot (JESD204B and Gapped Clocking)........................... 101

Distribution Embedded Output Clock Modulation................ 105

Modulation Controller Overview .......................................... 105

Modulation Magnitude ........................................................... 105

Modulation Period................................................................... 107

Balanced and Unbalanced Modulation................................. 107

Modulation Synchronization.................................................. 109

Modulation Trigger.................................................................. 110

Distribution Output Clock Synchronization............................ 111

Synchronization Overview...................................................... 111

Output Signals After Power-Up or Reset.............................. 111

Manual Synchronization Trigger........................................... 111

Autoreconfiguration Synchronization Trigger.................... 111

Autosynchronization Trigger................................................. 112

Reference Synchronization ..................................................... 112

Frequency Translation Loops..................................................... 113

Frequency Translation Loops Overview............................... 113

Translation Profiles.................................................................. 113

Profile Enable............................................................................ 114

Profile Priority .......................................................................... 114

Input Reference Source Selection .......................................... 114

Active Reference Indication.................................................... 114

Translation Modes ................................................................... 115

Phase Buildout Mode............................................................... 116

Internal Zero Delay (Hitless) Mode ...................................... 117

External Zero Delay (Hitless) Mode...................................... 118

Source Profiles ..............................................................................119

Source Profiles Overview ........................................................ 119

DPLL Phase/Frequency Lock Detector................................. 119

Phase Step Limit ....................................................................... 119

Skew Adjustment ..................................................................... 120

Initial Phase Skew Refinement Steps..................................... 120

Digital PLL (DPLL)...................................................................... 122

DPLL Overview ........................................................................ 122

DPLL Loop Controller ............................................................ 122

DPLL Feedback Divider (N Divider) .................................... 123

DPLL Loop Filter ..................................................................... 124

DPLL NCO................................................................................ 126

NCO Gain Tuning Word Filter Bandwidth......................... 127

DPLL Lock Detectors .............................................................. 128

Freerun Tuning Word............................................................. 129

DPLL Fast Acquisition Options............................................. 130

DPLL Phase Offset Control .................................................... 132

Tuning Word Offset Clamp ................................................... 133

Phase Slew Rate Limit.............................................................. 134

Tuning Word History.............................................................. 135

Delay Compensation ............................................................... 138

Time Stamp Tagging Options ................................................ 140

Cascaded DPLL Configuration .................................................. 141

Caveats of Cascaded DPLL Operation.................................. 143

Analog PLL (APLL) ..................................................................... 144

APLL Overview ........................................................................ 144

Voltage Controlled Oscillator (VCO)................................... 144

APLL Feedback Divider (M Divider).................................... 145

Phase Frequency Detector (PFD) .......................................... 145

Charge Pump............................................................................ 145

APLL Loop Filter...................................................................... 146

Reference Switching..................................................................... 147

Reference Switching Overview............................................... 147

Forced Freerun Mode.............................................................. 147

Forced Holdover Mode ........................................................... 147

Manual/Automatic Translation Profile Selection ............... 147

Time to Digital Converter (TDC).............................................. 154

Time Stamps ................................................................................. 155

Time Stamps Overview ........................................................... 155

Digital Crosspoint Mux........................................................... 155

Tagged Time Stamps ............................................................... 156

User Time Stamp Processor (UTSP)......................................... 157

UTSP Overview ........................................................................ 157

Reading User Time Stamps .................................................... 157

Interpreting User Time Stamps ............................................. 158

AD9546/PCBZ 数据表(PDF) 4 Page - Analog Devices

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