AD9546SLASHPCBZ datasheet(70/205 Pages) AD

70 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 70 of 205

PARAMETER DESTINATION SELECTION

IUTS 0 and IUTS 1 each require the following two parameters

from the register map as part of normal operation: time code

and restart.

The register map has one instance of the two parameters which

the user designates for a specific IUTS via the 5-bit unsigned

destination bit field in Bits[4:0] of Register 0x0F09. The

destination bits select the desired path of the two parameters to

the target resource (via the two 1 to 4 demuxes shown in Figure 54)

according to Table 45. The target resources include both IUTSs

as well as the CCS. For destination bit field values of 30 and 31,

see the Synchronization Time section of the Common Clock

Synchronizer (CCS) section for details.

Table 45. Destination Selection

Destination Bit Field Value (Decimal)

Target Resource

0 to 12

Reserved

IUTS 0

IUTS 1

15 to 29

Reserved

CCS Sync 0 time code

CCS Sync 1 time code

TIME CODE AND FORMAT

The time code and format functionality is identical to that

described in the Synchronization Time section of the Common

Clock Synchronizer (CCS) section. The only difference is that

the user selects IUTS 0 or IUTS 1 as the target resource per

Table 45 via Bits[4:0] of Register 0x0F09.

IUTS TIME OFFSET

Each IUTS allow the user to add a constant time offset value to

each estimated time code generated by the IUTS period

processor. The time offset programs as a 24-bit signed value in

The time offset carries units of 2−48 sec, yielding a range of

approximately ±29.8 ns. For example, to program a time offset

of 5 ns (5 × 10−9 sec), first convert to the appropriate units and

round the result to the nearest integer as follows:

5 × 10−9 × 248 = 1,407,375

This value in 24-bit hexadecimal format is: 0x 15 798F.

IUTS STATUS

When the IUTS period processor establishes the period

associated with successive time codes, it indicates a ready status

(Logic 1) via Bits[1:0] of Register 0x3023, with Bit 1 and Bit 0

indicating the status of IUTS 1 and IUTS 0, respectively.

However, the user can manually override the valid status of an

IUTS (see the Declaring an IUTS Invalid section).

The user also has access to two IRQ status bits for each IUTS

via Bits[3:0] of Register 0x301E. One bit of the pair indicates

IUTS valid status, and the other bit indicates IUTS invalid

status. IUTS valid status appears in Bit 0 and Bit 2 (for IUTS 0

and IUTS 1, respectively). IUTS invalid status appears in Bit 1 and

Bit 3 (for IUTS 0 and IUTS 1, respectively).

The status bits exist as part of the IRQ mechanism (see the

Interrupt Request (IRQ) section). IUTS status indication is also

available via an appropriately configured Mx status pin (see the

Status and Control Pins section).

An IUTS indicates invalid status under the following conditions:

•

The user declares an IUTS as invalid (see the Declaring an

IUTS section)

•

The common clock DPLL indicates unlocked (unless the

user activates the bypass lock option (see the IUTS Bypass

Lock Option section)

•

A restart (see the IUTS Restart section) accompanies an

input time code

•

An input time code arrives when the IUTS is busy

•

The IUTS period monitor detects a period discontinuity

IUTS RESTART

The IUTS period processor uses an internal algorithm for filtering

period jitter that may be present on the incoming sequence of time

codes. The algorithm gradually reduces the filtering bandwidth

as it collects period samples over time. In some cases, there may

be a need to restart the filtering process (such as the user

switching the IUTS to a new time code source, for example).

To restart the IUTS, use the restart bit in Bit 0 of Register 0x0F08.

Logic 0 (default) is normal operation, whereas Logic 1 forces

the IUTS to restart.

IUTS BYPASS LOCK OPTION

Normally, each IUTS requires the common clock DPLL to

indicate locked status to processes time codes. The user,

however, can remove this constraint for each IUTS

independently via Bit 1 of Register 0x0F00 for IUTS 0 and

inoperative when the common clock DPLL indicates an unlock

condition. Logic 1 causes the IUTS to disregard the lock status

of the common clock DPLL.

DECLARING AN IUTS INVALID

Because the output of an IUTS is a digitized clock signal

available to other digitized clocking resources, the user may

need to declare an IUTS as an invalid clock source. For

example, the user may be aware of a problem with the source of

input time codes to the IUTS that renders the IUTS output

unsuitable as a digitized clock source to downstream resources.

To handle such conditions, each IUTS allows manual

invalidation of an IUTS as a time stamp source.

To invalidate an IUTS, use Bit 0 of Register 0x0F00 for IUTS 0 and

IUTS, whereas Logic 1 allows normal IUTS operation. Note

that manual invalidation of an IUTS causes the IUTS to

indicate an invalid status (see the IUTS Status section).

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