AD9546SLASHPCBZ datasheet(92/205 Pages) AD

92 / 205 page

AD9546

Data Sheet

Rev. 0 | Page 92 of 205

In single-divider differential mode, the clock signal at the

OUTxyN pin phase is inverted relative to the OUTxyP pin. In

single-divider single-ended mode, the clock signals at the

OUTxyP and OUTxyN pins are in phase relative to one

another. In dual-divider single-ended mode, the Qxy divider

drives the OUTxyP pin and the Qxyy divider drives the

OUTxyN pin. In this mode, each output of the subgroup can

have a different frequency and phase offset.

OUTPUT DRIVER CONFIGURATIONS

Each driver receives a clock input signal from its associated

channel divider (see Figure 66). The current source (or sink) of

the driver is either on or off, depending on the logic level

output by the divider. That is, when the divider output is

Logic 0, the driver output current is 0 mA. Conversely, when

the divider output is Logic 1, the drive output current is the

programmed output current value. The Qxy divider has normal

and inverted logic outputs, which means when the Qxy divider

connects to both drivers and one current source is on, the other

is off, allowing a differential output signal.

Differential HCSL Output

To drive a standard HCSL receiver, refer to Figure 39. This

configuration requires programming the driver settings as

follows: single-divider, differential drivers; current source;

driver current = 15 mA. In this mode, the driver expects a 50 Ω

termination to ground on each driver output pin. The 15 mA

drive current yields 750 mV swing across each 50 Ω load.

LVDS Output

To drive an LVDS receiver using ac coupling, refer to Figure 38.

This configuration requires programming the driver settings as

follows: single-divider, differential drivers; current source; and

driver current = 7.5 mA. In this mode, the driver expects a 50 Ω

termination to ground on each driver output pin and dc

blocking capacitors with a 100 Ω differential termination at the

receiver. The expected termination arrangement yields 188 mV

swing across the 100 Ω load but with 188 mV common mode

across the output pins, and thus, the need for dc blocking

capacitors to preserve the common-mode bias of 1.2 V of the

receiver.

To drive an LVDS receiver directly with dc coupling, use a

T network, as shown in Figure 41. This configuration requires

programming the driver settings as follows: single-divider,

differential drivers; current sink; and driver current = 7.5 mA.

This arrangement yields a 375 mV swing across the output pins

with 1.24 V common mode. When using an additional 100 Ω

differential termination (RL) at the receiver, however, ac coupling

is necessary (as shown in Figure 38). The additional termination

also requires programming a drive current of 15 mA. This

arrangement yields a 375 mV swing across the output pins with

0.67 V common mode (thus, the ac coupling requirement to

preserve the 1.2 V common-mode bias of the LVDS receiver).

To drive an LVDS receiver using a Thevenin equivalent

termination, refer to Figure 42, which exhibits the equivalent of

a 50 Ω pull-up resistor to 1.42 V on each output pin. This

configuration requires programming the driver settings as

follows: single-divider, differential drivers; current sink; and

driver current = 7.5 mA. This arrangement yields a 375 mV

swing across the output pins with 1.23 V common mode.

When using an additional 100 Ω differential termination (RL) at

the receiver, however, ac coupling is necessary (as shown in

Figure 38), as well as programming a drive current of 15 mA.

This arrangement yields 375 mV swing across the output pins

with 1.05 V common mode (thus the ac coupling requirement

to preserve the 1.2 V common-mode bias of the LVDS receiver).

To drive an LVDS-compatible receiver that can handle boosted

signal swing, use a Thevenin equivalent termination per Figure 43,

which exhibits the equivalent of a 50 Ω pull-up resistor to

1.60 V on each output pin. This configuration requires

programming the driver settings as follows: single-divider,

differential drivers; current sink; and driver current = 15 mA.

This arrangement yields 750 mV swing across the output pins

with 1.23 V common mode.

CML Output

To configure an output for CML signals, see Figure 40. When

using a 50 Ω pull-up resistor to 1.2 V, this configuration

requires programming the driver settings as follows: single-

divider, differential drivers; current sink; and driver current =

7.5 mA. This arrangement yields a 375 mV swing across the

output pins with 1.01 V common mode.

When using a 50 Ω pull-up resistor to 1.5 V or 1.8 V, program

a drive current of 15 mA. This arrangement yields a 750 mV

swing across the output pins with 1.125 V common mode for a

1.5 V supply and 1.425 V common mode for a 1.8 V supply.

Dual, Single-Ended, In Phase Outputs

To configure the output to produce the same signal (in phase)

on each pin of an OUTxyP/OUTxyN pin pair, refer to Figure 44.

This configuration requires programming the driver settings as

follows: single-divider, single-ended drivers and current source.

Select the driver current to yield an acceptable voltage swing

based on the load resistance, RL. The output is essentially a

current source (on or off per the logic state of the Qxy divider

output) with an external pull-down resistor. Thus, the output

signal swing is between ground and V = I × RL.

Independent, Single-Ended Outputs

To configure the output to produce independent signals on the

two output pins of an OUTxyP/OUTxyN pin pair, refer to

Figure 46. This configuration requires programming the driver

settings as follows: dual-divider, single-ended drivers and

current source. Select the driver current to yield an acceptable

voltage swing based on the load resistance, RL. Note that the

output is essentially a current source (on or off per the logic

state of the Qxy and Qxyy dividers) with an external pull-down

resistor. Thus, the output signal swing is between ground and V =

I × RL.

AD9546/PCBZ 数据表(PDF) 92 Page - Analog Devices

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